// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.10.3.144
// Netlist written on Tue Oct 18 09:10:10 2022
//
// Verilog Description of module top
//

module top (clk, led, pwma, pwmb, en, tx, rx) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(1[8:11])
    input clk;   // f:/home/mini-step-fpga/prj/pwm/top.v(3[8:11])
    output led;   // f:/home/mini-step-fpga/prj/pwm/top.v(5[9:12])
    output pwma;   // f:/home/mini-step-fpga/prj/pwm/top.v(7[13:17])
    output pwmb;   // f:/home/mini-step-fpga/prj/pwm/top.v(8[13:17])
    output en;   // f:/home/mini-step-fpga/prj/pwm/top.v(10[13:15])
    output tx;   // f:/home/mini-step-fpga/prj/pwm/top.v(12[9:11])
    input rx;   // f:/home/mini-step-fpga/prj/pwm/top.v(13[8:10])
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(3[8:11])
    
    wire GND_net, VCC_net, led_c, pwma_c, pwmb_c, en_c, tx_c, 
        rx_c, rst_n;
    wire [7:0]cmd;   // f:/home/mini-step-fpga/prj/pwm/top.v(20[19:22])
    
    wire wr;
    wire [31:0]wr_data;   // f:/home/mini-step-fpga/prj/pwm/top.v(22[12:19])
    wire [31:0]cmd_data;   // f:/home/mini-step-fpga/prj/pwm/top.v(23[13:21])
    
    wire valid_o;
    wire [2:0]led_status;   // f:/home/mini-step-fpga/prj/pwm/top.v(27[11:21])
    wire [31:0]tcr;   // f:/home/mini-step-fpga/prj/pwm/top.v(39[12:15])
    wire [31:0]hcra;   // f:/home/mini-step-fpga/prj/pwm/top.v(39[18:22])
    wire [31:0]hcrb;   // f:/home/mini-step-fpga/prj/pwm/top.v(39[25:29])
    wire [31:0]pwmcnt;   // f:/home/mini-step-fpga/prj/pwm/top.v(40[11:17])
    
    wire n9, n4966, n5387, pwma_N_332, pwma_N_330, pwmb_N_336, pwmb_N_334, 
        n32, n42, n5380, n40, n38, n6043, n10, n12, n8, n18, 
        n4836, n5373, n24, n25, n5428, n36, n24_adj_970, n6042, 
        n48, n22, n20, n50, n18_adj_971, n16, n52, n14, n4, 
        n11, n9_adj_972, n8_adj_973, n6, n6_adj_974, n4_adj_975, 
        n56, n14_adj_976, n5362, n62, n60, n58, n56_adj_977, n54, 
        n52_adj_978, n50_adj_979, n62_adj_980, n5358, n4957, n62_adj_981, 
        n60_adj_982, n58_adj_983, n5353, n54_adj_984, n52_adj_985, 
        n50_adj_986, n40_adj_987, n4955, n11_adj_988, n36_adj_989, 
        n4827, n5344, n8_adj_990, clk_c_enable_133, n10_adj_991, n60_adj_992, 
        n34, n58_adj_993, n32_adj_994, n30, n5337, n5430, n5333, 
        n4948, n5331, n38_adj_995, n28, n42_adj_996, n54_adj_997, 
        clk_c_enable_121, clk_c_enable_90, clk_c_enable_213, clk_c_enable_215, 
        n40_adj_998, n26, n25_adj_999, n4_adj_1000, n24_adj_1001, 
        n6_adj_1002, n22_adj_1003, n6041, n14_adj_1004, n16_adj_1005, 
        n20_adj_1006, n12_adj_1007, n3413, n26_adj_1008, n28_adj_1009, 
        n36_adj_1010, n34_adj_1011, n5319, n32_adj_1012, n4941, n30_adj_1013, 
        n38_adj_1014, n34_adj_1015, n20_adj_1016, n6040, n42_adj_1017, 
        n44, n5312, n6039, n5310, n18_adj_1018, n44_adj_1019, n46, 
        n28_adj_1020, n46_adj_1021, n16_adj_1022, n48_adj_1023, n14_adj_1024, 
        n26_adj_1025, n25_adj_1026, n46_adj_1027, n5432, n5302, n5300, 
        n12_adj_1028, n4937, n3832, n4777, n3831, n3830, n3829, 
        n3828, n3827, n3826, n3825, n3824, n3823, n3822, n5295, 
        n3821, n3820, n3819, n11_adj_1029, n10_adj_1030, n9_adj_1031, 
        n48_adj_1032, n3818, n3817, n5421, n30_adj_1033, n5289, 
        n984, n22_adj_1034, n54_adj_1035, n56_adj_1036, n1165, n1164, 
        n1163, n1136, n1162, n1161, n1160, n1159, n1158, n1157, 
        n1135, n1137, n1138, n1139, n1140, n1141, n1142, n1143, 
        n1144, n1145, n5277, n44_adj_1037, n1156, n1134, n1146, 
        n1147, n1148, n1149, n1150, n1151, n1152, n1155, n1154, 
        n1153, n134, n135, n136, n137, n138, n139, n140, n141, 
        n142, n143, n144, n145, n146, n147, n148, n149, n150, 
        n151, n152, n153, n154, n155, n156, n157, n158, n159, 
        n160, n161, n162, n163, n164, n165, n5270, n5268, n5264, 
        n4926, n5254, n4923, n5249, n4814, n5239, n6036, n6035, 
        n5232, n5228, n4916, n5215, n6033, n6032, n5204, n4911, 
        n5438, n5197, n5440, n5193, n5442, n4906, n5182, n4904, 
        n5180, n5446, n5175, n6031, n6030, n4899, n6029, n42_adj_1038, 
        n41, n52_adj_1039, n5164, n6028, n5155, n6026, n5153, 
        n6025, n50_adj_1040, n38_adj_1041, n34_adj_1042, n5448, n5146, 
        n6024, n5139, n4884, n5135, n4881, n5124, n5121, n6023, 
        n62_adj_1043, n5114, n6022, n6021, n5109, n60_adj_1044, 
        n5450, n5104, n5102, n58_adj_1045, n5097, n57, n4874, 
        n56_adj_1046, n6020, n4872, n54_adj_1047, n5082, n6019, 
        n5079, n52_adj_1048, n6018, n5072, n6017, n5070, n50_adj_1049, 
        n5059, n5056, n6016, n46_adj_1050, n4861, n6091, n6090, 
        n5044, n6089, n6088, n6015, n6087, n5041, n6086, n6085, 
        n6084, n4858, n5034, n6083, n6082, n42_adj_1051, n6081, 
        n6080, n6079, n41_adj_1052, n5025, n6014, n6078, n6077, 
        n5993, n6013, n6012, n38_adj_1053, n6076, n6075, n5012, 
        n6074, n6073, n6072, n6071, n6070, n6069, n6068, n5003, 
        n6011, n6010, n5457, n34_adj_1054, n4999, n6067, n6065, 
        n6064, n46_adj_1055, n4995, n4846, n6063, n6062, n6061, 
        n6060, n6059, n6058, n6009, n6711, n6057, n4805, n6056, 
        n6055, n62_adj_1056, n4843, n4984, n6054, n60_adj_1057, 
        n4982, n58_adj_1058, n6001, n6053, clk_c_enable_290, n6052, 
        n57_adj_1059, n56_adj_1060, n6051, n5464, n4977, n6050, 
        n5395, n6049, n5998, n6048, n5391, n6047, n6046, n6045, 
        n6044;
    
    LUT4 i3596_2_lut_3_lut_4_lut (.A(pwmcnt[10]), .B(hcrb[10]), .C(hcrb[11]), 
         .D(pwmcnt[11]), .Z(n4843)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3596_2_lut_3_lut_4_lut.init = 16'h9009;
    IB rx_pad (.I(rx), .O(rx_c));   // f:/home/mini-step-fpga/prj/pwm/top.v(13[8:10])
    LUT4 i9_2_lut (.A(hcrb[27]), .B(hcrb[30]), .Z(n41_adj_1052)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i9_2_lut.init = 16'heeee;
    LUT4 i28_4_lut (.A(hcrb[10]), .B(n56_adj_1046), .C(n46_adj_1050), 
         .D(hcrb[20]), .Z(n60_adj_1044)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i28_4_lut.init = 16'hfffe;
    LUT4 i4245_4_lut (.A(n6070), .B(n6069), .C(n6068), .D(n4966), .Z(n5457)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4245_4_lut.init = 16'hefee;
    LUT4 i3719_4_lut (.A(n6082), .B(n6081), .C(n25_adj_1026), .D(n4843), 
         .Z(n4966)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3719_4_lut.init = 16'h1011;
    LUT4 LessThan_4_i35_2_lut_rep_262 (.A(tcr[17]), .B(pwmcnt[17]), .Z(n6024)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i35_2_lut_rep_262.init = 16'h6666;
    LUT4 LessThan_4_i30_3_lut_3_lut (.A(tcr[17]), .B(pwmcnt[17]), .C(n12_adj_1028), 
         .Z(n30)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i30_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i22_4_lut (.A(hcrb[19]), .B(hcrb[5]), .C(hcrb[22]), .D(hcrb[6]), 
         .Z(n54_adj_1047)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i22_4_lut.init = 16'hfffe;
    LUT4 LessThan_4_i37_2_lut_rep_263 (.A(tcr[18]), .B(pwmcnt[18]), .Z(n6025)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i37_2_lut_rep_263.init = 16'h6666;
    FD1P3IX led_status__i0 (.D(cmd_data[0]), .SP(clk_c_enable_215), .CD(n6065), 
            .CK(clk_c), .Q(led_status[0]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam led_status__i0.GSR = "DISABLED";
    LUT4 i10_2_lut (.A(hcrb[7]), .B(hcrb[14]), .Z(n42_adj_1051)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i10_2_lut.init = 16'heeee;
    LUT4 i24_4_lut (.A(hcrb[29]), .B(hcrb[3]), .C(hcrb[13]), .D(hcrb[31]), 
         .Z(n56_adj_1046)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i24_4_lut.init = 16'hfffe;
    LUT4 i4252_4_lut (.A(n6011), .B(n6010), .C(n6014), .D(n5362), .Z(n5464)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4252_4_lut.init = 16'hefee;
    IB clk_pad (.I(clk), .O(clk_c));   // f:/home/mini-step-fpga/prj/pwm/top.v(3[8:11])
    FD1P3IX tcr__i0 (.D(cmd_data[0]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[0]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i0.GSR = "DISABLED";
    LUT4 i4115_4_lut (.A(n6013), .B(n6012), .C(n25_adj_999), .D(n5239), 
         .Z(n5362)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4115_4_lut.init = 16'h1011;
    OB tx_pad (.I(tx_c), .O(tx));   // f:/home/mini-step-fpga/prj/pwm/top.v(12[9:11])
    LUT4 i14_2_lut (.A(hcrb[15]), .B(hcrb[23]), .Z(n46_adj_1050)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i14_2_lut.init = 16'heeee;
    FD1P3IX hcrb__i0 (.D(cmd_data[0]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[0]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i0.GSR = "DISABLED";
    LUT4 i20_4_lut (.A(hcrb[17]), .B(hcrb[1]), .C(hcrb[24]), .D(hcrb[4]), 
         .Z(n52_adj_1048)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i20_4_lut.init = 16'hfffe;
    LUT4 LessThan_4_i39_2_lut_rep_264 (.A(tcr[19]), .B(pwmcnt[19]), .Z(n6026)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i39_2_lut_rep_264.init = 16'h6666;
    FD1P3IX hcra__i0 (.D(cmd_data[0]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[0]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i0.GSR = "DISABLED";
    OB en_pad (.I(en_c), .O(en));   // f:/home/mini-step-fpga/prj/pwm/top.v(10[13:15])
    OB pwmb_pad (.I(pwmb_c), .O(pwmb));   // f:/home/mini-step-fpga/prj/pwm/top.v(8[13:17])
    OB pwma_pad (.I(pwma_c), .O(pwma));   // f:/home/mini-step-fpga/prj/pwm/top.v(7[13:17])
    OB led_pad (.I(led_c), .O(led));   // f:/home/mini-step-fpga/prj/pwm/top.v(5[9:12])
    LUT4 i6_2_lut (.A(hcrb[9]), .B(hcrb[12]), .Z(n38_adj_1053)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i6_2_lut.init = 16'heeee;
    LUT4 i4228_4_lut (.A(n6074), .B(n6073), .C(n6072), .D(n4881), .Z(n5440)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4228_4_lut.init = 16'hefee;
    LUT4 i4048_2_lut_3_lut_4_lut (.A(tcr[19]), .B(pwmcnt[19]), .C(pwmcnt[18]), 
         .D(tcr[18]), .Z(n5295)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4048_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 LessThan_4_i32_3_lut_3_lut (.A(tcr[19]), .B(pwmcnt[19]), .C(pwmcnt[18]), 
         .Z(n32_adj_994)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i32_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_i9_2_lut (.A(pwmcnt[4]), .B(hcrb[4]), .Z(n9_adj_972)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i9_2_lut.init = 16'h6666;
    LUT4 i4216_4_lut (.A(n6086), .B(n6085), .C(n6084), .D(n4923), .Z(n5428)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4216_4_lut.init = 16'hefee;
    LUT4 pwmcnt_31__I_0_i25_2_lut (.A(pwmcnt[12]), .B(hcrb[12]), .Z(n25_adj_1026)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i25_2_lut.init = 16'h6666;
    FD1S3IX pwmcnt_402__i0 (.D(n165), .CK(clk_c), .CD(n984), .Q(pwmcnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i0.GSR = "DISABLED";
    LUT4 i4218_4_lut (.A(n6026), .B(n6025), .C(n6024), .D(n5277), .Z(n5430)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4218_4_lut.init = 16'hefee;
    LUT4 m1_lut (.Z(n6711)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
    defparam m1_lut.init = 16'hffff;
    FD1P3IX hcra__i31 (.D(cmd_data[31]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[31]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i31.GSR = "DISABLED";
    LUT4 i4209_4_lut (.A(n6016), .B(n6015), .C(n6020), .D(n5319), .Z(n5421)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4209_4_lut.init = 16'hefee;
    LUT4 i4236_4_lut (.A(n6046), .B(n6051), .C(n6050), .D(n5079), .Z(n5448)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4236_4_lut.init = 16'hefee;
    FD1P3IX hcra__i30 (.D(cmd_data[30]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[30]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i30.GSR = "DISABLED";
    LUT4 pwmcnt_31__I_0_i11_2_lut (.A(pwmcnt[5]), .B(hcrb[5]), .Z(n11)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i11_2_lut.init = 16'h6666;
    FD1P3IX hcra__i29 (.D(cmd_data[29]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[29]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i29.GSR = "DISABLED";
    FD1P3AX pwmb_57 (.D(pwmb_N_334), .SP(rst_n), .CK(clk_c), .Q(pwmb_c));   // f:/home/mini-step-fpga/prj/pwm/top.v(41[8] 51[4])
    defparam pwmb_57.GSR = "DISABLED";
    LUT4 LessThan_4_i4_4_lut (.A(pwmcnt[0]), .B(pwmcnt[1]), .C(tcr[1]), 
         .D(tcr[0]), .Z(n4)) /* synthesis lut_function=(A (B+!(C))+!A !(B (C (D))+!B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i4_4_lut.init = 16'h8ecf;
    LUT4 i4234_4_lut (.A(n6057), .B(n6056), .C(n6055), .D(n5121), .Z(n5446)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4234_4_lut.init = 16'hefee;
    LUT4 i4225_4_lut (.A(n6039), .B(n6042), .C(n6041), .D(n25), .Z(n5197)) /* synthesis lut_function=(A+!(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4225_4_lut.init = 16'haaab;
    LUT4 i4244_4_lut (.A(n6067), .B(n6070), .C(n6069), .D(n25_adj_1026), 
         .Z(n4999)) /* synthesis lut_function=(A+!(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4244_4_lut.init = 16'haaab;
    LUT4 i4251_4_lut (.A(n6009), .B(n6011), .C(n6010), .D(n25_adj_999), 
         .Z(n5395)) /* synthesis lut_function=(A+!(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4251_4_lut.init = 16'haaab;
    LUT4 LessThan_4_i17_2_lut_rep_266 (.A(tcr[8]), .B(pwmcnt[8]), .Z(n6028)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i17_2_lut_rep_266.init = 16'h6666;
    LUT4 LessThan_4_i8_3_lut_3_lut (.A(tcr[8]), .B(pwmcnt[8]), .C(pwmcnt[4]), 
         .Z(n8_adj_990)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i8_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i19_2_lut_rep_267 (.A(tcr[9]), .B(pwmcnt[9]), .Z(n6029)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i19_2_lut_rep_267.init = 16'h6666;
    LUT4 i4072_2_lut_3_lut_4_lut (.A(tcr[9]), .B(pwmcnt[9]), .C(pwmcnt[21]), 
         .D(tcr[21]), .Z(n5319)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4072_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 LessThan_4_i21_2_lut_rep_268 (.A(tcr[10]), .B(pwmcnt[10]), .Z(n6030)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i21_2_lut_rep_268.init = 16'h6666;
    LUT4 LessThan_4_i23_2_lut_rep_269 (.A(tcr[11]), .B(pwmcnt[11]), .Z(n6031)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i23_2_lut_rep_269.init = 16'h6666;
    LUT4 i3992_2_lut_3_lut_4_lut (.A(tcr[11]), .B(pwmcnt[11]), .C(pwmcnt[10]), 
         .D(tcr[10]), .Z(n5239)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i3992_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 LessThan_4_i18_3_lut_3_lut (.A(tcr[11]), .B(pwmcnt[11]), .C(pwmcnt[10]), 
         .Z(n18_adj_1018)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i18_3_lut_3_lut.init = 16'hd4d4;
    FD1P3AX pwma_56 (.D(pwma_N_330), .SP(rst_n), .CK(clk_c), .Q(pwma_c));   // f:/home/mini-step-fpga/prj/pwm/top.v(41[8] 51[4])
    defparam pwma_56.GSR = "DISABLED";
    LUT4 LessThan_4_i27_2_lut_rep_270 (.A(tcr[13]), .B(pwmcnt[13]), .Z(n6032)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i27_2_lut_rep_270.init = 16'h6666;
    FD1S3IX wr_58 (.D(valid_o), .CK(clk_c), .CD(n6065), .Q(wr));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_58.GSR = "DISABLED";
    LUT4 pwmcnt_31__I_0_i4_4_lut (.A(hcrb[0]), .B(hcrb[1]), .C(pwmcnt[1]), 
         .D(pwmcnt[0]), .Z(n4_adj_975)) /* synthesis lut_function=(A (B+!(C))+!A !(B (C (D))+!B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i4_4_lut.init = 16'h8ecf;
    FD1P3IX wr_data__i0 (.D(n1165), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[0]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i0.GSR = "DISABLED";
    LUT4 LessThan_4_i7_2_lut_rep_271 (.A(tcr[3]), .B(pwmcnt[3]), .Z(n6033)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i7_2_lut_rep_271.init = 16'h6666;
    LUT4 i2277_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[31]), 
         .Z(n1134)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2277_2_lut_4_lut.init = 16'hfe00;
    LUT4 LessThan_4_i6_3_lut_3_lut (.A(tcr[3]), .B(pwmcnt[3]), .C(pwmcnt[2]), 
         .Z(n6)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i6_3_lut_3_lut.init = 16'hd4d4;
    FD1P3IX hcra__i28 (.D(cmd_data[28]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[28]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i28.GSR = "DISABLED";
    FD1P3IX hcra__i27 (.D(cmd_data[27]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[27]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i27.GSR = "DISABLED";
    LUT4 LessThan_4_i13_2_lut_rep_273 (.A(tcr[6]), .B(pwmcnt[6]), .Z(n6035)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i13_2_lut_rep_273.init = 16'h6666;
    FD1P3IX hcra__i26 (.D(cmd_data[26]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[26]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i26.GSR = "DISABLED";
    FD1P3IX hcra__i25 (.D(cmd_data[25]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[25]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i25.GSR = "DISABLED";
    FD1P3IX hcra__i24 (.D(cmd_data[24]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[24]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i24.GSR = "DISABLED";
    FD1P3IX hcra__i23 (.D(cmd_data[23]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[23]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i23.GSR = "DISABLED";
    FD1P3IX hcra__i22 (.D(cmd_data[22]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[22]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i22.GSR = "DISABLED";
    FD1P3IX hcra__i21 (.D(cmd_data[21]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[21]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i21.GSR = "DISABLED";
    FD1P3IX hcra__i20 (.D(cmd_data[20]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[20]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i20.GSR = "DISABLED";
    FD1P3IX hcra__i19 (.D(cmd_data[19]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[19]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i19.GSR = "DISABLED";
    FD1P3IX hcra__i18 (.D(cmd_data[18]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[18]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i18.GSR = "DISABLED";
    FD1P3IX hcra__i17 (.D(cmd_data[17]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[17]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i17.GSR = "DISABLED";
    FD1P3IX hcra__i16 (.D(cmd_data[16]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[16]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i16.GSR = "DISABLED";
    LUT4 LessThan_4_i10_3_lut_3_lut (.A(tcr[6]), .B(pwmcnt[6]), .C(pwmcnt[5]), 
         .Z(n10_adj_1030)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i10_3_lut_3_lut.init = 16'hd4d4;
    FD1P3IX hcra__i15 (.D(cmd_data[15]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[15]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i15.GSR = "DISABLED";
    FD1P3IX hcra__i14 (.D(cmd_data[14]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[14]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i14.GSR = "DISABLED";
    FD1P3IX hcra__i13 (.D(cmd_data[13]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[13]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i13.GSR = "DISABLED";
    FD1P3IX hcra__i12 (.D(cmd_data[12]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[12]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i12.GSR = "DISABLED";
    FD1P3IX hcra__i11 (.D(cmd_data[11]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[11]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i11.GSR = "DISABLED";
    FD1P3IX hcra__i10 (.D(cmd_data[10]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[10]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i10.GSR = "DISABLED";
    FD1P3IX hcra__i9 (.D(cmd_data[9]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[9]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i9.GSR = "DISABLED";
    FD1P3IX hcra__i8 (.D(cmd_data[8]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[8]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i8.GSR = "DISABLED";
    FD1P3IX hcra__i7 (.D(cmd_data[7]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[7]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i7.GSR = "DISABLED";
    FD1P3IX hcra__i6 (.D(cmd_data[6]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[6]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i6.GSR = "DISABLED";
    FD1P3IX hcra__i5 (.D(cmd_data[5]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[5]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i5.GSR = "DISABLED";
    FD1P3IX hcra__i4 (.D(cmd_data[4]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[4]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i4.GSR = "DISABLED";
    FD1P3IX hcra__i3 (.D(cmd_data[3]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[3]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i3.GSR = "DISABLED";
    FD1P3IX hcra__i2 (.D(cmd_data[2]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[2]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i2.GSR = "DISABLED";
    FD1P3IX hcra__i1 (.D(cmd_data[1]), .SP(clk_c_enable_90), .CD(n6065), 
            .CK(clk_c), .Q(hcra[1]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcra__i1.GSR = "DISABLED";
    FD1P3IX hcrb__i31 (.D(cmd_data[31]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[31]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i31.GSR = "DISABLED";
    FD1P3IX hcrb__i30 (.D(cmd_data[30]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[30]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i30.GSR = "DISABLED";
    FD1P3IX hcrb__i29 (.D(cmd_data[29]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[29]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i29.GSR = "DISABLED";
    FD1P3IX hcrb__i28 (.D(cmd_data[28]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[28]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i28.GSR = "DISABLED";
    FD1P3IX hcrb__i27 (.D(cmd_data[27]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[27]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i27.GSR = "DISABLED";
    FD1P3IX hcrb__i26 (.D(cmd_data[26]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[26]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i26.GSR = "DISABLED";
    FD1P3IX hcrb__i25 (.D(cmd_data[25]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[25]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i25.GSR = "DISABLED";
    FD1P3IX hcrb__i24 (.D(cmd_data[24]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[24]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i24.GSR = "DISABLED";
    FD1P3IX hcrb__i23 (.D(cmd_data[23]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[23]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i23.GSR = "DISABLED";
    FD1P3IX hcrb__i22 (.D(cmd_data[22]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[22]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i22.GSR = "DISABLED";
    FD1P3IX hcrb__i21 (.D(cmd_data[21]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[21]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i21.GSR = "DISABLED";
    FD1P3IX hcrb__i20 (.D(cmd_data[20]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[20]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i20.GSR = "DISABLED";
    FD1P3IX hcrb__i19 (.D(cmd_data[19]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[19]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i19.GSR = "DISABLED";
    FD1P3IX hcrb__i18 (.D(cmd_data[18]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[18]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i18.GSR = "DISABLED";
    FD1P3IX hcrb__i17 (.D(cmd_data[17]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[17]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i17.GSR = "DISABLED";
    FD1P3IX hcrb__i16 (.D(cmd_data[16]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[16]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i16.GSR = "DISABLED";
    FD1P3IX hcrb__i15 (.D(cmd_data[15]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[15]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i15.GSR = "DISABLED";
    FD1P3IX hcrb__i14 (.D(cmd_data[14]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[14]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i14.GSR = "DISABLED";
    FD1P3IX hcrb__i13 (.D(cmd_data[13]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[13]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i13.GSR = "DISABLED";
    FD1P3IX hcrb__i12 (.D(cmd_data[12]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[12]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i12.GSR = "DISABLED";
    FD1P3IX hcrb__i11 (.D(cmd_data[11]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[11]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i11.GSR = "DISABLED";
    FD1P3IX hcrb__i10 (.D(cmd_data[10]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[10]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i10.GSR = "DISABLED";
    FD1P3IX hcrb__i9 (.D(cmd_data[9]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[9]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i9.GSR = "DISABLED";
    FD1P3IX hcrb__i8 (.D(cmd_data[8]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[8]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i8.GSR = "DISABLED";
    FD1P3IX hcrb__i7 (.D(cmd_data[7]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[7]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i7.GSR = "DISABLED";
    FD1P3IX hcrb__i6 (.D(cmd_data[6]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[6]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i6.GSR = "DISABLED";
    FD1P3IX hcrb__i5 (.D(cmd_data[5]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[5]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i5.GSR = "DISABLED";
    FD1P3IX hcrb__i4 (.D(cmd_data[4]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[4]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i4.GSR = "DISABLED";
    FD1P3IX hcrb__i3 (.D(cmd_data[3]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[3]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i3.GSR = "DISABLED";
    FD1P3IX hcrb__i2 (.D(cmd_data[2]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[2]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i2.GSR = "DISABLED";
    FD1P3IX hcrb__i1 (.D(cmd_data[1]), .SP(clk_c_enable_121), .CD(n6065), 
            .CK(clk_c), .Q(hcrb[1]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam hcrb__i1.GSR = "DISABLED";
    LUT4 LessThan_4_i15_2_lut_rep_274 (.A(tcr[7]), .B(pwmcnt[7]), .Z(n6036)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i15_2_lut_rep_274.init = 16'h6666;
    FD1P3IX en_64 (.D(cmd_data[0]), .SP(clk_c_enable_133), .CD(n6065), 
            .CK(clk_c), .Q(en_c));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam en_64.GSR = "DISABLED";
    LUT4 i4030_2_lut_3_lut_4_lut (.A(tcr[7]), .B(pwmcnt[7]), .C(pwmcnt[16]), 
         .D(tcr[16]), .Z(n5277)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4030_2_lut_3_lut_4_lut.init = 16'h9009;
    FD1P3IX tcr__i31 (.D(cmd_data[31]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[31]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i31.GSR = "DISABLED";
    FD1P3IX tcr__i30 (.D(cmd_data[30]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[30]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i30.GSR = "DISABLED";
    FD1P3IX tcr__i29 (.D(cmd_data[29]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[29]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i29.GSR = "DISABLED";
    FD1P3IX tcr__i28 (.D(cmd_data[28]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[28]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i28.GSR = "DISABLED";
    FD1P3IX tcr__i27 (.D(cmd_data[27]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[27]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i27.GSR = "DISABLED";
    FD1P3IX tcr__i26 (.D(cmd_data[26]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[26]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i26.GSR = "DISABLED";
    FD1P3IX tcr__i25 (.D(cmd_data[25]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[25]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i25.GSR = "DISABLED";
    FD1P3IX tcr__i24 (.D(cmd_data[24]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[24]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i24.GSR = "DISABLED";
    FD1P3IX tcr__i23 (.D(cmd_data[23]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[23]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i23.GSR = "DISABLED";
    FD1P3IX tcr__i22 (.D(cmd_data[22]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[22]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i22.GSR = "DISABLED";
    FD1P3IX tcr__i21 (.D(cmd_data[21]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[21]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i21.GSR = "DISABLED";
    FD1P3IX tcr__i20 (.D(cmd_data[20]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[20]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i20.GSR = "DISABLED";
    FD1P3IX tcr__i19 (.D(cmd_data[19]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[19]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i19.GSR = "DISABLED";
    FD1P3IX tcr__i18 (.D(cmd_data[18]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[18]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i18.GSR = "DISABLED";
    FD1P3IX tcr__i17 (.D(cmd_data[17]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[17]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i17.GSR = "DISABLED";
    FD1P3IX tcr__i16 (.D(cmd_data[16]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[16]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i16.GSR = "DISABLED";
    FD1P3IX tcr__i15 (.D(cmd_data[15]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[15]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i15.GSR = "DISABLED";
    FD1P3IX tcr__i14 (.D(cmd_data[14]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[14]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i14.GSR = "DISABLED";
    FD1P3IX tcr__i13 (.D(cmd_data[13]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[13]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i13.GSR = "DISABLED";
    FD1P3IX tcr__i12 (.D(cmd_data[12]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[12]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i12.GSR = "DISABLED";
    FD1P3IX tcr__i11 (.D(cmd_data[11]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[11]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i11.GSR = "DISABLED";
    FD1P3IX tcr__i10 (.D(cmd_data[10]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[10]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i10.GSR = "DISABLED";
    FD1P3IX tcr__i9 (.D(cmd_data[9]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[9]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i9.GSR = "DISABLED";
    FD1P3IX tcr__i8 (.D(cmd_data[8]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[8]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i8.GSR = "DISABLED";
    FD1P3IX tcr__i7 (.D(cmd_data[7]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[7]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i7.GSR = "DISABLED";
    FD1P3IX tcr__i6 (.D(cmd_data[6]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[6]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i6.GSR = "DISABLED";
    FD1P3IX tcr__i5 (.D(cmd_data[5]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[5]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i5.GSR = "DISABLED";
    FD1P3IX tcr__i4 (.D(cmd_data[4]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[4]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i4.GSR = "DISABLED";
    FD1P3IX tcr__i3 (.D(cmd_data[3]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[3]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i3.GSR = "DISABLED";
    FD1P3IX tcr__i2 (.D(cmd_data[2]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[2]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i2.GSR = "DISABLED";
    FD1P3IX tcr__i1 (.D(cmd_data[1]), .SP(clk_c_enable_213), .CD(n6065), 
            .CK(clk_c), .Q(tcr[1]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam tcr__i1.GSR = "DISABLED";
    FD1P3IX led_status__i2 (.D(cmd_data[2]), .SP(clk_c_enable_215), .CD(n6065), 
            .CK(clk_c), .Q(led_status[2]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam led_status__i2.GSR = "DISABLED";
    FD1P3IX led_status__i1 (.D(cmd_data[1]), .SP(clk_c_enable_215), .CD(n6065), 
            .CK(clk_c), .Q(led_status[1]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam led_status__i1.GSR = "DISABLED";
    GSR GSR_INST (.GSR(rst_n));
    LUT4 i2276_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[30]), 
         .Z(n1135)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2276_2_lut_4_lut.init = 16'hfe00;
    FD1S3IX pwmcnt_402__i1 (.D(n164), .CK(clk_c), .CD(n984), .Q(pwmcnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i1.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i2 (.D(n163), .CK(clk_c), .CD(n984), .Q(pwmcnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i2.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i3 (.D(n162), .CK(clk_c), .CD(n984), .Q(pwmcnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i3.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i4 (.D(n161), .CK(clk_c), .CD(n984), .Q(pwmcnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i4.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i5 (.D(n160), .CK(clk_c), .CD(n984), .Q(pwmcnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i5.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i6 (.D(n159), .CK(clk_c), .CD(n984), .Q(pwmcnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i6.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i7 (.D(n158), .CK(clk_c), .CD(n984), .Q(pwmcnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i7.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i8 (.D(n157), .CK(clk_c), .CD(n984), .Q(pwmcnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i8.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i9 (.D(n156), .CK(clk_c), .CD(n984), .Q(pwmcnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i9.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i10 (.D(n155), .CK(clk_c), .CD(n984), .Q(pwmcnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i10.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i11 (.D(n154), .CK(clk_c), .CD(n984), .Q(pwmcnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i11.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i12 (.D(n153), .CK(clk_c), .CD(n984), .Q(pwmcnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i12.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i13 (.D(n152), .CK(clk_c), .CD(n984), .Q(pwmcnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i13.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i14 (.D(n151), .CK(clk_c), .CD(n984), .Q(pwmcnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i14.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i15 (.D(n150), .CK(clk_c), .CD(n984), .Q(pwmcnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i15.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i16 (.D(n149), .CK(clk_c), .CD(n984), .Q(pwmcnt[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i16.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i17 (.D(n148), .CK(clk_c), .CD(n984), .Q(pwmcnt[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i17.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i18 (.D(n147), .CK(clk_c), .CD(n984), .Q(pwmcnt[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i18.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i19 (.D(n146), .CK(clk_c), .CD(n984), .Q(pwmcnt[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i19.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i20 (.D(n145), .CK(clk_c), .CD(n984), .Q(pwmcnt[20])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i20.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i21 (.D(n144), .CK(clk_c), .CD(n984), .Q(pwmcnt[21])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i21.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i22 (.D(n143), .CK(clk_c), .CD(n984), .Q(pwmcnt[22])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i22.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i23 (.D(n142), .CK(clk_c), .CD(n984), .Q(pwmcnt[23])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i23.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i24 (.D(n141), .CK(clk_c), .CD(n984), .Q(pwmcnt[24])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i24.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i25 (.D(n140), .CK(clk_c), .CD(n984), .Q(pwmcnt[25])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i25.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i26 (.D(n139), .CK(clk_c), .CD(n984), .Q(pwmcnt[26])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i26.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i27 (.D(n138), .CK(clk_c), .CD(n984), .Q(pwmcnt[27])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i27.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i28 (.D(n137), .CK(clk_c), .CD(n984), .Q(pwmcnt[28])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i28.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i29 (.D(n136), .CK(clk_c), .CD(n984), .Q(pwmcnt[29])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i29.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i30 (.D(n135), .CK(clk_c), .CD(n984), .Q(pwmcnt[30])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i30.GSR = "DISABLED";
    FD1S3IX pwmcnt_402__i31 (.D(n134), .CK(clk_c), .CD(n984), .Q(pwmcnt[31])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402__i31.GSR = "DISABLED";
    LUT4 pwmcnt_31__I_0_i10_3_lut_3_lut (.A(pwmcnt[6]), .B(hcrb[6]), .C(hcrb[5]), 
         .Z(n10)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i10_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_68_i63_2_lut_rep_277 (.A(pwmcnt[31]), .B(hcra[31]), 
         .Z(n6039)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i63_2_lut_rep_277.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i56_3_lut_3_lut (.A(pwmcnt[31]), .B(hcra[31]), 
         .C(n18), .Z(n56_adj_977)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i56_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwma_I_1_4_lut (.A(n57_adj_1059), .B(pwma_N_332), .C(n62_adj_1056), 
         .D(n58_adj_1058), .Z(pwma_N_330)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[11:40])
    defparam pwma_I_1_4_lut.init = 16'hccc8;
    LUT4 i25_4_lut (.A(hcra[0]), .B(n50_adj_1040), .C(n34_adj_1042), .D(hcra[28]), 
         .Z(n57_adj_1059)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i25_4_lut.init = 16'hfffe;
    CCU2D pwmcnt_402_add_4_33 (.A0(pwmcnt[31]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3832), .S0(n134));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_33.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_33.INIT1 = 16'h0000;
    defparam pwmcnt_402_add_4_33.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_33.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_31 (.A0(pwmcnt[29]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[30]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3831), .COUT(n3832), .S0(n136), .S1(n135));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_31.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_31.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_31.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_31.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_29 (.A0(pwmcnt[27]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[28]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3830), .COUT(n3831), .S0(n138), .S1(n137));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_29.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_29.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_29.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_29.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_27 (.A0(pwmcnt[25]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[26]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3829), .COUT(n3830), .S0(n140), .S1(n139));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_27.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_27.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_27.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_27.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_25 (.A0(pwmcnt[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[24]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3828), .COUT(n3829), .S0(n142), .S1(n141));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_25.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_25.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_25.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_25.INJECT1_1 = "NO";
    LUT4 pwmcnt_31__I_0_68_i64_4_lut (.A(n40_adj_998), .B(n62), .C(n6039), 
         .D(n5180), .Z(pwma_N_332)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i64_4_lut.init = 16'hcacc;
    CCU2D pwmcnt_402_add_4_23 (.A0(pwmcnt[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[22]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3827), .COUT(n3828), .S0(n144), .S1(n143));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_23.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_23.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_23.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_23.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_21 (.A0(pwmcnt[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[20]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3826), .COUT(n3827), .S0(n146), .S1(n145));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_21.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_21.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_21.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_21.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_19 (.A0(pwmcnt[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[18]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3825), .COUT(n3826), .S0(n148), .S1(n147));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_19.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_19.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_19.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_19.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_17 (.A0(pwmcnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[16]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3824), .COUT(n3825), .S0(n150), .S1(n149));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_17.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_17.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_17.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_17.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_15 (.A0(pwmcnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[14]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3823), .COUT(n3824), .S0(n152), .S1(n151));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_15.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_15.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_15.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_15.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_13 (.A0(pwmcnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[12]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3822), .COUT(n3823), .S0(n154), .S1(n153));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_13.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_13.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_13.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_13.INJECT1_1 = "NO";
    LUT4 i30_4_lut (.A(n41), .B(n60_adj_1057), .C(n54_adj_1035), .D(n42_adj_1038), 
         .Z(n62_adj_1056)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i30_4_lut.init = 16'hfffe;
    CCU2D pwmcnt_402_add_4_11 (.A0(pwmcnt[9]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[10]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3821), .COUT(n3822), .S0(n156), .S1(n155));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_11.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_11.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_11.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_11.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_9 (.A0(pwmcnt[7]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[8]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3820), .COUT(n3821), .S0(n158), .S1(n157));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_9.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_9.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_9.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_9.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_7 (.A0(pwmcnt[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3819), .COUT(n3820), .S0(n160), .S1(n159));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_7.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_7.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_7.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_7.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_5 (.A0(pwmcnt[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3818), .COUT(n3819), .S0(n162), .S1(n161));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_5.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_5.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_5.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_5.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_3 (.A0(pwmcnt[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3817), .COUT(n3818), .S0(n164), .S1(n163));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_3.INIT0 = 16'hfaaa;
    defparam pwmcnt_402_add_4_3.INIT1 = 16'hfaaa;
    defparam pwmcnt_402_add_4_3.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_3.INJECT1_1 = "NO";
    CCU2D pwmcnt_402_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(pwmcnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n3817), .S1(n165));   // f:/home/mini-step-fpga/prj/pwm/top.v(45[39:52])
    defparam pwmcnt_402_add_4_1.INIT0 = 16'hF000;
    defparam pwmcnt_402_add_4_1.INIT1 = 16'h0555;
    defparam pwmcnt_402_add_4_1.INJECT1_0 = "NO";
    defparam pwmcnt_402_add_4_1.INJECT1_1 = "NO";
    LUT4 i26_4_lut (.A(hcra[25]), .B(n52_adj_1039), .C(n38_adj_1041), 
         .D(hcra[26]), .Z(n58_adj_1058)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i26_4_lut.init = 16'hfffe;
    LUT4 i4227_2_lut_3_lut (.A(pwmcnt[31]), .B(hcra[31]), .C(n5438), .Z(n5193)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4227_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i18_4_lut (.A(hcra[8]), .B(hcra[11]), .C(hcra[16]), .D(hcra[21]), 
         .Z(n50_adj_1040)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i18_4_lut.init = 16'hfffe;
    LUT4 pwmcnt_31__I_0_68_i57_2_lut_rep_278 (.A(pwmcnt[28]), .B(hcra[28]), 
         .Z(n6040)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i57_2_lut_rep_278.init = 16'h6666;
    LUT4 i2_2_lut (.A(hcra[18]), .B(hcra[2]), .Z(n34_adj_1042)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i2_2_lut.init = 16'heeee;
    LUT4 pwmcnt_31__I_0_68_i62_4_lut (.A(n48_adj_1032), .B(n60), .C(n6039), 
         .D(n5182), .Z(n62)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i62_4_lut.init = 16'hcacc;
    LUT4 i3933_4_lut (.A(n6042), .B(n6041), .C(n6040), .D(n5153), .Z(n5180)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3933_4_lut.init = 16'h0100;
    LUT4 i3935_4_lut (.A(n6042), .B(n6041), .C(n6040), .D(n5155), .Z(n5182)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3935_4_lut.init = 16'h0100;
    LUT4 i4233_2_lut_3_lut_4_lut (.A(pwmcnt[28]), .B(hcra[28]), .C(n6053), 
         .D(n6054), .Z(n5175)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4233_2_lut_3_lut_4_lut.init = 16'hfff6;
    LUT4 i3906_4_lut (.A(n6054), .B(n6053), .C(n6052), .D(n5124), .Z(n5153)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3906_4_lut.init = 16'h0100;
    LUT4 i3877_4_lut (.A(n6057), .B(n6056), .C(n6055), .D(n5109), .Z(n5124)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3877_4_lut.init = 16'h0100;
    LUT4 i3862_4_lut (.A(n6063), .B(n6047), .C(n6046), .D(n5082), .Z(n5109)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3862_4_lut.init = 16'h5455;
    LUT4 pwmcnt_31__I_0_68_i50_3_lut_3_lut (.A(pwmcnt[28]), .B(hcra[28]), 
         .C(n22_adj_1034), .Z(n50_adj_979)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i50_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i3835_4_lut (.A(n6051), .B(n6050), .C(n6049), .D(n5059), .Z(n5082)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3835_4_lut.init = 16'h0100;
    LUT4 i3812_4_lut (.A(n6045), .B(n6044), .C(n6043), .D(n5044), .Z(n5059)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3812_4_lut.init = 16'h0001;
    LUT4 i3797_4_lut (.A(n25), .B(n6062), .C(n6058), .D(n5025), .Z(n5044)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3797_4_lut.init = 16'h0100;
    LUT4 i3778_4_lut (.A(n6061), .B(n6060), .C(n6059), .D(n5012), .Z(n5025)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3778_4_lut.init = 16'h1011;
    FD1P3IX wr_data__i1 (.D(n1164), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[1]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i1.GSR = "DISABLED";
    LUT4 i2215_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[4]), 
         .Z(n1161)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2215_2_lut_4_lut.init = 16'hff01;
    LUT4 i3765_4_lut (.A(n6048), .B(n11_adj_988), .C(n9), .D(n5003), 
         .Z(n5012)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3765_4_lut.init = 16'h1011;
    FD1P3IX wr_data__i2 (.D(n1163), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[2]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i2.GSR = "DISABLED";
    FD1P3IX wr_data__i3 (.D(n1162), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[3]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i3.GSR = "DISABLED";
    FD1P3IX wr_data__i4 (.D(n1161), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[4]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i4.GSR = "DISABLED";
    FD1P3IX wr_data__i5 (.D(n1160), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[5]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i5.GSR = "DISABLED";
    FD1P3IX wr_data__i6 (.D(n1159), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[6]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i6.GSR = "DISABLED";
    FD1P3IX wr_data__i7 (.D(n1158), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[7]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i7.GSR = "DISABLED";
    FD1P3IX wr_data__i8 (.D(n1157), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[8]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i8.GSR = "DISABLED";
    FD1P3IX wr_data__i9 (.D(n1156), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[9]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i9.GSR = "DISABLED";
    FD1P3IX wr_data__i10 (.D(n1155), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[10]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i10.GSR = "DISABLED";
    FD1P3IX wr_data__i11 (.D(n1154), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[11]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i11.GSR = "DISABLED";
    FD1P3IX wr_data__i12 (.D(n1153), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[12]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i12.GSR = "DISABLED";
    FD1P3IX wr_data__i13 (.D(n1152), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[13]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i13.GSR = "DISABLED";
    FD1P3IX wr_data__i14 (.D(n1151), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[14]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i14.GSR = "DISABLED";
    FD1P3IX wr_data__i15 (.D(n1150), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[15]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i15.GSR = "DISABLED";
    FD1P3IX wr_data__i16 (.D(n1149), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[16]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i16.GSR = "DISABLED";
    FD1P3IX wr_data__i17 (.D(n1148), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[17]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i17.GSR = "DISABLED";
    FD1P3IX wr_data__i18 (.D(n1147), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[18]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i18.GSR = "DISABLED";
    FD1P3IX wr_data__i19 (.D(n1146), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[19]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i19.GSR = "DISABLED";
    FD1P3IX wr_data__i20 (.D(n1145), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[20]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i20.GSR = "DISABLED";
    FD1P3IX wr_data__i21 (.D(n1144), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[21]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i21.GSR = "DISABLED";
    FD1P3IX wr_data__i22 (.D(n1143), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[22]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i22.GSR = "DISABLED";
    FD1P3IX wr_data__i23 (.D(n1142), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[23]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i23.GSR = "DISABLED";
    FD1P3IX wr_data__i24 (.D(n1141), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[24]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i24.GSR = "DISABLED";
    FD1P3IX wr_data__i25 (.D(n1140), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[25]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i25.GSR = "DISABLED";
    FD1P3IX wr_data__i26 (.D(n1139), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[26]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i26.GSR = "DISABLED";
    FD1P3IX wr_data__i27 (.D(n1138), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[27]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i27.GSR = "DISABLED";
    FD1P3IX wr_data__i28 (.D(n1137), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[28]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i28.GSR = "DISABLED";
    FD1P3IX wr_data__i29 (.D(n1136), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[29]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i29.GSR = "DISABLED";
    FD1P3IX wr_data__i30 (.D(n1135), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[30]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i30.GSR = "DISABLED";
    FD1P3IX wr_data__i31 (.D(n1134), .SP(clk_c_enable_290), .CD(n6065), 
            .CK(clk_c), .Q(wr_data[31]));   // f:/home/mini-step-fpga/prj/pwm/top.v(55[8] 82[4])
    defparam wr_data__i31.GSR = "DISABLED";
    LUT4 pwmcnt_31__I_0_68_i59_2_lut_rep_279 (.A(pwmcnt[29]), .B(hcra[29]), 
         .Z(n6041)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i59_2_lut_rep_279.init = 16'h6666;
    LUT4 i3908_4_lut (.A(n6054), .B(n6053), .C(n6052), .D(n5135), .Z(n5155)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3908_4_lut.init = 16'h1011;
    LUT4 i3888_4_lut (.A(n6057), .B(n6056), .C(n6055), .D(n5114), .Z(n5135)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3888_4_lut.init = 16'h0100;
    LUT4 pwmcnt_31__I_0_68_i20_3_lut_3_lut (.A(pwmcnt[29]), .B(hcra[29]), 
         .C(hcra[12]), .Z(n20_adj_1006)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i20_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i3867_4_lut (.A(n6063), .B(n25), .C(n6062), .D(n5034), .Z(n5114)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3867_4_lut.init = 16'h5455;
    LUT4 i3787_4_lut (.A(n6058), .B(n6061), .C(n6060), .D(n9), .Z(n5034)) /* synthesis lut_function=(!(A+!(B+(C+(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3787_4_lut.init = 16'h5554;
    LUT4 i418_4_lut (.A(n5993), .B(rst_n), .C(cmd[1]), .D(cmd[0]), .Z(clk_c_enable_215)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (B))) */ ;
    defparam i418_4_lut.init = 16'h3b33;
    LUT4 i9_2_lut_adj_68 (.A(hcra[27]), .B(hcra[30]), .Z(n41)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i9_2_lut_adj_68.init = 16'heeee;
    LUT4 i28_4_lut_adj_69 (.A(hcra[10]), .B(n56_adj_1060), .C(n46_adj_1055), 
         .D(hcra[20]), .Z(n60_adj_1057)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i28_4_lut_adj_69.init = 16'hfffe;
    LUT4 i22_4_lut_adj_70 (.A(hcra[19]), .B(hcra[5]), .C(hcra[22]), .D(hcra[6]), 
         .Z(n54_adj_1035)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i22_4_lut_adj_70.init = 16'hfffe;
    LUT4 i10_2_lut_adj_71 (.A(hcra[7]), .B(hcra[14]), .Z(n42_adj_1038)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i10_2_lut_adj_71.init = 16'heeee;
    LUT4 pwmcnt_31__I_0_68_i61_2_lut_rep_280 (.A(pwmcnt[30]), .B(hcra[30]), 
         .Z(n6042)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i61_2_lut_rep_280.init = 16'h6666;
    LUT4 i24_4_lut_adj_72 (.A(hcra[29]), .B(hcra[3]), .C(hcra[13]), .D(hcra[31]), 
         .Z(n56_adj_1060)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i24_4_lut_adj_72.init = 16'hfffe;
    LUT4 i14_2_lut_adj_73 (.A(hcra[15]), .B(hcra[23]), .Z(n46_adj_1055)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i14_2_lut_adj_73.init = 16'heeee;
    LUT4 pwmcnt_31__I_0_68_i54_3_lut_3_lut (.A(pwmcnt[30]), .B(hcra[30]), 
         .C(n20_adj_1006), .Z(n54)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i54_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i20_4_lut_adj_74 (.A(hcra[17]), .B(hcra[1]), .C(hcra[24]), .D(hcra[4]), 
         .Z(n52_adj_1039)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i20_4_lut_adj_74.init = 16'hfffe;
    LUT4 pwmcnt_31__I_0_68_i27_2_lut_rep_281 (.A(pwmcnt[13]), .B(hcra[13]), 
         .Z(n6043)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i27_2_lut_rep_281.init = 16'h6666;
    LUT4 i3_4_lut (.A(cmd[4]), .B(cmd[6]), .C(cmd[5]), .D(cmd[7]), .Z(n14_adj_976)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(74[5:9])
    defparam i3_4_lut.init = 16'hfffe;
    LUT4 i6_2_lut_adj_75 (.A(hcra[9]), .B(hcra[12]), .Z(n38_adj_1041)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[12:19])
    defparam i6_2_lut_adj_75.init = 16'heeee;
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    LUT4 i4243_2_lut_3_lut_4_lut (.A(pwmcnt[13]), .B(hcra[13]), .C(n6045), 
         .D(n6044), .Z(n5070)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4243_2_lut_3_lut_4_lut.init = 16'hfff6;
    LUT4 pwmcnt_31__I_0_68_i25_2_lut (.A(pwmcnt[12]), .B(hcra[12]), .Z(n25)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i25_2_lut.init = 16'h6666;
    LUT4 i2214_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[5]), 
         .Z(n1160)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2214_2_lut_4_lut.init = 16'hff01;
    LUT4 pwmcnt_31__I_0_68_i29_2_lut_rep_282 (.A(pwmcnt[14]), .B(hcra[14]), 
         .Z(n6044)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i29_2_lut_rep_282.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i14_3_lut_3_lut (.A(pwmcnt[14]), .B(hcra[14]), 
         .C(hcra[13]), .Z(n14_adj_1004)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i14_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_68_i31_2_lut_rep_283 (.A(pwmcnt[15]), .B(hcra[15]), 
         .Z(n6045)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i31_2_lut_rep_283.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i26_3_lut_3_lut (.A(pwmcnt[15]), .B(hcra[15]), 
         .C(n14_adj_1004), .Z(n26_adj_1008)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i26_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_68_i9_2_lut (.A(pwmcnt[4]), .B(hcra[4]), .Z(n9)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i9_2_lut.init = 16'h6666;
    LUT4 i2218_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[3]), 
         .Z(n1162)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2218_2_lut_4_lut.init = 16'hfe00;
    LUT4 i1_2_lut_rep_236 (.A(cmd[1]), .B(n14_adj_976), .Z(n5998)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i1_2_lut_rep_236.init = 16'heeee;
    LUT4 pwmcnt_31__I_0_68_i39_2_lut_rep_284 (.A(pwmcnt[19]), .B(hcra[19]), 
         .Z(n6046)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i39_2_lut_rep_284.init = 16'h6666;
    LUT4 i2219_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[2]), 
         .Z(n1163)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2219_2_lut_4_lut.init = 16'hfe00;
    LUT4 pwmcnt_31__I_0_68_i32_3_lut_3_lut (.A(pwmcnt[19]), .B(hcra[19]), 
         .C(hcra[18]), .Z(n32)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i32_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_68_i41_2_lut_rep_285 (.A(pwmcnt[20]), .B(hcra[20]), 
         .Z(n6047)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i41_2_lut_rep_285.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i11_2_lut (.A(pwmcnt[5]), .B(hcra[5]), .Z(n11_adj_988)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i11_2_lut.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i34_3_lut_3_lut (.A(pwmcnt[20]), .B(hcra[20]), 
         .C(n32), .Z(n34_adj_1015)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i34_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i2220_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[1]), 
         .Z(n1164)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2220_2_lut_4_lut.init = 16'hfe00;
    LUT4 i4239_2_lut_3_lut (.A(pwmcnt[20]), .B(hcra[20]), .C(n5450), .Z(n5102)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4239_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i4237_2_lut_3_lut (.A(pwmcnt[20]), .B(hcra[20]), .C(n5448), .Z(n5104)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4237_2_lut_3_lut.init = 16'hf6f6;
    LUT4 pwmcnt_31__I_0_68_i13_2_lut_rep_286 (.A(pwmcnt[6]), .B(hcra[6]), 
         .Z(n6048)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i13_2_lut_rep_286.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i10_3_lut_3_lut (.A(pwmcnt[6]), .B(hcra[6]), 
         .C(hcra[5]), .Z(n10_adj_991)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i10_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_68_i33_2_lut_rep_287 (.A(pwmcnt[16]), .B(hcra[16]), 
         .Z(n6049)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i33_2_lut_rep_287.init = 16'h6666;
    LUT4 i2206_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[0]), 
         .Z(n1165)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2206_2_lut_4_lut.init = 16'hfe00;
    LUT4 i2213_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[6]), 
         .Z(n1159)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2213_2_lut_4_lut.init = 16'hfe00;
    LUT4 pwmcnt_31__I_0_68_i12_3_lut_3_lut (.A(pwmcnt[16]), .B(hcra[16]), 
         .C(hcra[7]), .Z(n12_adj_1007)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i12_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i2212_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[7]), 
         .Z(n1158)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2212_2_lut_4_lut.init = 16'hfe00;
    LUT4 i2207_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[8]), 
         .Z(n1157)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2207_2_lut_4_lut.init = 16'hfe00;
    LUT4 pwmcnt_31__I_0_68_i35_2_lut_rep_288 (.A(pwmcnt[17]), .B(hcra[17]), 
         .Z(n6050)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i35_2_lut_rep_288.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i30_3_lut_3_lut (.A(pwmcnt[17]), .B(hcra[17]), 
         .C(n12_adj_1007), .Z(n30_adj_1033)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i30_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_68_i37_2_lut_rep_289 (.A(pwmcnt[18]), .B(hcra[18]), 
         .Z(n6051)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i37_2_lut_rep_289.init = 16'h6666;
    LUT4 i3850_2_lut_3_lut_4_lut (.A(pwmcnt[18]), .B(hcra[18]), .C(hcra[19]), 
         .D(pwmcnt[19]), .Z(n5097)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3850_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 pwmcnt_31__I_0_68_i51_2_lut_rep_290 (.A(pwmcnt[25]), .B(hcra[25]), 
         .Z(n6052)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i51_2_lut_rep_290.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i44_3_lut_3_lut (.A(pwmcnt[25]), .B(hcra[25]), 
         .C(n42_adj_1017), .Z(n44)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i44_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i4235_2_lut_3_lut (.A(pwmcnt[25]), .B(hcra[25]), .C(n5446), .Z(n5146)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4235_2_lut_3_lut.init = 16'hf6f6;
    LUT4 pwmcnt_31__I_0_68_i53_2_lut_rep_291 (.A(pwmcnt[26]), .B(hcra[26]), 
         .Z(n6053)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i53_2_lut_rep_291.init = 16'h6666;
    LUT4 i4111_4_lut (.A(n6014), .B(n6013), .C(n6012), .D(n5331), .Z(n5358)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4111_4_lut.init = 16'h0100;
    LUT4 i4084_4_lut (.A(n6017), .B(n6016), .C(n6015), .D(n5310), .Z(n5331)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4084_4_lut.init = 16'h0100;
    LUT4 i4063_4_lut (.A(n6020), .B(n6019), .C(n6018), .D(n5289), .Z(n5310)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4063_4_lut.init = 16'h1011;
    LUT4 pwmcnt_31__I_0_68_i55_2_lut_rep_292 (.A(pwmcnt[27]), .B(hcra[27]), 
         .Z(n6054)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i55_2_lut_rep_292.init = 16'h6666;
    LUT4 i4042_4_lut (.A(n6026), .B(n6025), .C(n6024), .D(n5264), .Z(n5289)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4042_4_lut.init = 16'h0100;
    LUT4 i4017_4_lut (.A(n6023), .B(n6022), .C(n6021), .D(n5249), .Z(n5264)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4017_4_lut.init = 16'h0100;
    LUT4 i4002_4_lut (.A(n6032), .B(n25_adj_999), .C(n6031), .D(n5228), 
         .Z(n5249)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4002_4_lut.init = 16'h5455;
    LUT4 i4212_4_lut (.A(cmd[0]), .B(cmd[3]), .C(n3413), .D(n5998), 
         .Z(clk_c_enable_133)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i4212_4_lut.init = 16'h0020;
    LUT4 i3981_4_lut (.A(n6030), .B(n6029), .C(n6028), .D(n5215), .Z(n5228)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i3981_4_lut.init = 16'h0001;
    LUT4 i1_2_lut_rep_239 (.A(valid_o), .B(n14_adj_976), .Z(n6001)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut_rep_239.init = 16'h2222;
    LUT4 i3968_4_lut (.A(n6036), .B(n6035), .C(n11_adj_1029), .D(n5204), 
         .Z(n5215)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i3968_4_lut.init = 16'h0001;
    L6MUX21 pwmcnt_31__I_0_i40 (.D0(n28_adj_1020), .D1(n38_adj_995), .SD(n4904), 
            .Z(n40_adj_987));
    L6MUX21 LessThan_4_i40 (.D0(n28), .D1(n38), .SD(n5300), .Z(n40));
    L6MUX21 pwmcnt_31__I_0_68_i40 (.D0(n28_adj_1009), .D1(n38_adj_1014), 
            .SD(n5102), .Z(n40_adj_998));
    LUT4 pwmcnt_31__I_0_68_i22_3_lut_3_lut (.A(pwmcnt[27]), .B(hcra[27]), 
         .C(hcra[26]), .Z(n22_adj_1034)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i22_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i3957_4_lut (.A(n9_adj_1031), .B(n6033), .C(tcr[2]), .D(pwmcnt[2]), 
         .Z(n5204)) /* synthesis lut_function=(!(A+(B+!(C (D)+!C !(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i3957_4_lut.init = 16'h1001;
    LUT4 pwmcnt_31__I_0_68_i45_2_lut_rep_293 (.A(pwmcnt[22]), .B(hcra[22]), 
         .Z(n6055)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i45_2_lut_rep_293.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i24_3_lut_3_lut (.A(pwmcnt[22]), .B(hcra[22]), 
         .C(n16_adj_1005), .Z(n24)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i24_3_lut_3_lut.init = 16'hd4d4;
    L6MUX21 pwmcnt_31__I_0_68_i60 (.D0(n52_adj_978), .D1(n58), .SD(n5193), 
            .Z(n60));
    LUT4 pwmcnt_31__I_0_68_i47_2_lut_rep_294 (.A(pwmcnt[23]), .B(hcra[23]), 
         .Z(n6056)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i47_2_lut_rep_294.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i49_2_lut_rep_295 (.A(pwmcnt[24]), .B(hcra[24]), 
         .Z(n6057)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i49_2_lut_rep_295.init = 16'h6666;
    LUT4 i3892_2_lut_3_lut_4_lut (.A(pwmcnt[24]), .B(hcra[24]), .C(hcra[23]), 
         .D(pwmcnt[23]), .Z(n5139)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3892_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 LessThan_4_i11_2_lut (.A(tcr[5]), .B(pwmcnt[5]), .Z(n11_adj_1029)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i11_2_lut.init = 16'h6666;
    L6MUX21 pwmcnt_31__I_0_i60 (.D0(n52_adj_985), .D1(n58_adj_983), .SD(n4995), 
            .Z(n60_adj_982));
    L6MUX21 LessThan_4_i60 (.D0(n52), .D1(n58_adj_993), .SD(n5391), .Z(n60_adj_992));
    LUT4 pwmcnt_31__I_0_68_i42_3_lut_3_lut (.A(pwmcnt[24]), .B(hcra[24]), 
         .C(hcra[23]), .Z(n42_adj_1017)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i42_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_68_i21_2_lut_rep_296 (.A(pwmcnt[10]), .B(hcra[10]), 
         .Z(n6058)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i21_2_lut_rep_296.init = 16'h6666;
    LUT4 LessThan_4_i9_2_lut (.A(tcr[4]), .B(pwmcnt[4]), .Z(n9_adj_1031)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i9_2_lut.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_68_i15_2_lut_rep_297 (.A(pwmcnt[7]), .B(hcra[7]), 
         .Z(n6059)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i15_2_lut_rep_297.init = 16'h6666;
    LUT4 i3832_2_lut_3_lut_4_lut (.A(pwmcnt[7]), .B(hcra[7]), .C(hcra[16]), 
         .D(pwmcnt[16]), .Z(n5079)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3832_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 pwmcnt_31__I_0_68_i17_2_lut_rep_298 (.A(pwmcnt[8]), .B(hcra[8]), 
         .Z(n6060)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i17_2_lut_rep_298.init = 16'h6666;
    PFUMX pwmcnt_31__I_0_i38 (.BLUT(n30_adj_1013), .ALUT(n36_adj_1010), 
          .C0(n4906), .Z(n38_adj_995));
    PFUMX pwmcnt_31__I_0_i48 (.BLUT(n24_adj_970), .ALUT(n46), .C0(n4948), 
          .Z(n48_adj_1023));
    LUT4 pwmcnt_31__I_0_68_i8_3_lut_3_lut (.A(pwmcnt[8]), .B(hcra[8]), .C(hcra[4]), 
         .Z(n8)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i8_3_lut_3_lut.init = 16'hd4d4;
    PFUMX LessThan_4_i38 (.BLUT(n30), .ALUT(n36_adj_989), .C0(n5302), 
          .Z(n38));
    LUT4 pwmcnt_31__I_0_68_i19_2_lut_rep_299 (.A(pwmcnt[9]), .B(hcra[9]), 
         .Z(n6061)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i19_2_lut_rep_299.init = 16'h6666;
    LUT4 i2205_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[9]), 
         .Z(n1156)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2205_2_lut_4_lut.init = 16'hfe00;
    PFUMX LessThan_4_i48 (.BLUT(n24_adj_1001), .ALUT(n46_adj_1021), .C0(n5344), 
          .Z(n48));
    LUT4 LessThan_4_i25_2_lut (.A(tcr[12]), .B(pwmcnt[12]), .Z(n25_adj_999)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i25_2_lut.init = 16'h6666;
    PFUMX pwmcnt_31__I_0_68_i38 (.BLUT(n30_adj_1033), .ALUT(n36), .C0(n5104), 
          .Z(n38_adj_1014));
    LUT4 i3756_3_lut_4_lut (.A(pwmcnt[3]), .B(hcra[3]), .C(hcra[2]), .D(pwmcnt[2]), 
         .Z(n5003)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3756_3_lut_4_lut.init = 16'h9009;
    PFUMX pwmcnt_31__I_0_68_i48 (.BLUT(n24), .ALUT(n46_adj_1027), .C0(n5146), 
          .Z(n48_adj_1032));
    LUT4 pwmcnt_31__I_0_68_i6_3_lut_3_lut (.A(pwmcnt[3]), .B(hcra[3]), .C(hcra[2]), 
         .Z(n6_adj_1002)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i6_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_68_i23_2_lut_rep_300 (.A(pwmcnt[11]), .B(hcra[11]), 
         .Z(n6062)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i23_2_lut_rep_300.init = 16'h6666;
    LUT4 i3794_2_lut_3_lut_4_lut (.A(pwmcnt[11]), .B(hcra[11]), .C(hcra[10]), 
         .D(pwmcnt[10]), .Z(n5041)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3794_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 pwmcnt_31__I_0_68_i18_3_lut_3_lut (.A(pwmcnt[11]), .B(hcra[11]), 
         .C(hcra[10]), .Z(n18)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i18_3_lut_3_lut.init = 16'hd4d4;
    PFUMX pwmcnt_31__I_0_68_i58 (.BLUT(n54), .ALUT(n56_adj_977), .C0(n5197), 
          .Z(n58));
    LUT4 pwmcnt_31__I_0_68_i43_2_lut_rep_301 (.A(pwmcnt[21]), .B(hcra[21]), 
         .Z(n6063)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i43_2_lut_rep_301.init = 16'h6666;
    LUT4 i3874_2_lut_3_lut_4_lut (.A(pwmcnt[21]), .B(hcra[21]), .C(hcra[9]), 
         .D(pwmcnt[9]), .Z(n5121)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3874_2_lut_3_lut_4_lut.init = 16'h9009;
    PFUMX pwmcnt_31__I_0_i58 (.BLUT(n54_adj_984), .ALUT(n56_adj_1036), .C0(n4999), 
          .Z(n58_adj_983));
    LUT4 i2199_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[10]), 
         .Z(n1155)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2199_2_lut_4_lut.init = 16'hfe00;
    LUT4 i2192_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[11]), 
         .Z(n1154)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2192_2_lut_4_lut.init = 16'hfe00;
    LUT4 pwmcnt_31__I_0_68_i16_3_lut_3_lut (.A(pwmcnt[21]), .B(hcra[21]), 
         .C(hcra[9]), .Z(n16_adj_1005)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i16_3_lut_3_lut.init = 16'hd4d4;
    LUT4 equal_23_i10_2_lut_rep_302 (.A(cmd[2]), .B(cmd[3]), .Z(n6064)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(73[5:9])
    defparam equal_23_i10_2_lut_rep_302.init = 16'heeee;
    VLO i1 (.Z(GND_net));
    LUT4 i1_2_lut_rep_231_3_lut_4_lut (.A(cmd[2]), .B(cmd[3]), .C(n14_adj_976), 
         .D(valid_o), .Z(n5993)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(73[5:9])
    defparam i1_2_lut_rep_231_3_lut_4_lut.init = 16'h0100;
    PFUMX LessThan_4_i58 (.BLUT(n54_adj_997), .ALUT(n56), .C0(n5395), 
          .Z(n58_adj_993));
    LUT4 LessThan_4_i22_3_lut_3_lut (.A(tcr[27]), .B(pwmcnt[27]), .C(pwmcnt[26]), 
         .Z(n22_adj_1003)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i22_3_lut_3_lut.init = 16'hd4d4;
    PFUMX pwmcnt_31__I_0_i28 (.BLUT(n4_adj_975), .ALUT(n26_adj_1025), .C0(n4872), 
          .Z(n28_adj_1020));
    LUT4 i2183_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[12]), 
         .Z(n1153)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2183_2_lut_4_lut.init = 16'hff01;
    LUT4 i4170_4_lut_4_lut (.A(n6052), .B(n5139), .C(n44), .D(n8), .Z(n46_adj_1027)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4170_4_lut_4_lut.init = 16'hf4b0;
    LUT4 i4172_4_lut_4_lut (.A(n6047), .B(n5097), .C(n34_adj_1015), .D(n10_adj_991), 
         .Z(n36)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4172_4_lut_4_lut.init = 16'hf4b0;
    LUT4 i4174_4_lut_4_lut (.A(n6017), .B(n5337), .C(n44_adj_1037), .D(n8_adj_990), 
         .Z(n46_adj_1021)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4174_4_lut_4_lut.init = 16'hf4b0;
    LUT4 i4176_4_lut_4_lut (.A(n6018), .B(n5295), .C(n34), .D(n10_adj_1030), 
         .Z(n36_adj_989)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4176_4_lut_4_lut.init = 16'hf4b0;
    LUT4 pwmcnt_31__I_0_i63_2_lut_rep_305 (.A(pwmcnt[31]), .B(hcrb[31]), 
         .Z(n6067)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i63_2_lut_rep_305.init = 16'h6666;
    LUT4 i4178_4_lut_4_lut (.A(n6080), .B(n4941), .C(n44_adj_1019), .D(n8_adj_973), 
         .Z(n46)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4178_4_lut_4_lut.init = 16'hf4b0;
    LUT4 i4180_4_lut_4_lut (.A(n6075), .B(n4899), .C(n34_adj_1011), .D(n10), 
         .Z(n36_adj_1010)) /* synthesis lut_function=(A (C)+!A (B (D)+!B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4180_4_lut_4_lut.init = 16'hf4b0;
    LUT4 pwmcnt_31__I_0_i56_3_lut_3_lut (.A(pwmcnt[31]), .B(hcrb[31]), .C(n18_adj_971), 
         .Z(n56_adj_1036)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i56_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i4246_2_lut_3_lut (.A(pwmcnt[31]), .B(hcrb[31]), .C(n5457), .Z(n4995)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4246_2_lut_3_lut.init = 16'hf6f6;
    LUT4 pwmcnt_31__I_0_i57_2_lut_rep_306 (.A(pwmcnt[28]), .B(hcrb[28]), 
         .Z(n6068)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i57_2_lut_rep_306.init = 16'h6666;
    LUT4 i4250_2_lut_3_lut_4_lut (.A(pwmcnt[28]), .B(hcrb[28]), .C(n6081), 
         .D(n6082), .Z(n4977)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4250_2_lut_3_lut_4_lut.init = 16'hfff6;
    LUT4 pwmcnt_31__I_0_i50_3_lut_3_lut (.A(pwmcnt[28]), .B(hcrb[28]), .C(n22), 
         .Z(n50_adj_986)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i50_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i2181_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[13]), 
         .Z(n1152)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2181_2_lut_4_lut.init = 16'hff01;
    LUT4 pwmcnt_31__I_0_i59_2_lut_rep_307 (.A(pwmcnt[29]), .B(hcrb[29]), 
         .Z(n6069)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i59_2_lut_rep_307.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_i20_3_lut_3_lut (.A(pwmcnt[29]), .B(hcrb[29]), .C(hcrb[12]), 
         .Z(n20)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i20_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_i61_2_lut_rep_308 (.A(pwmcnt[30]), .B(hcrb[30]), 
         .Z(n6070)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i61_2_lut_rep_308.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_i54_3_lut_3_lut (.A(pwmcnt[30]), .B(hcrb[30]), .C(n20), 
         .Z(n54_adj_984)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i54_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_i33_2_lut_rep_309 (.A(pwmcnt[16]), .B(hcrb[16]), 
         .Z(n6071)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i33_2_lut_rep_309.init = 16'h6666;
    PFUMX pwmcnt_31__I_0_i52 (.BLUT(n6_adj_974), .ALUT(n50_adj_986), .C0(n4977), 
          .Z(n52_adj_985));
    LUT4 pwmcnt_31__I_0_i12_3_lut_3_lut (.A(pwmcnt[16]), .B(hcrb[16]), .C(hcrb[7]), 
         .Z(n12)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i12_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_i35_2_lut_rep_310 (.A(pwmcnt[17]), .B(hcrb[17]), 
         .Z(n6072)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i35_2_lut_rep_310.init = 16'h6666;
    LUT4 i3530_3_lut (.A(cmd[0]), .B(cmd[3]), .C(cmd[1]), .Z(n4777)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i3530_3_lut.init = 16'hfefe;
    LUT4 pwmcnt_31__I_0_i30_3_lut_3_lut (.A(pwmcnt[17]), .B(hcrb[17]), .C(n12), 
         .Z(n30_adj_1013)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i30_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_i37_2_lut_rep_311 (.A(pwmcnt[18]), .B(hcrb[18]), 
         .Z(n6073)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i37_2_lut_rep_311.init = 16'h6666;
    PFUMX LessThan_4_i28 (.BLUT(n4), .ALUT(n26), .C0(n5268), .Z(n28));
    LUT4 pwmcnt_31__I_0_i39_2_lut_rep_312 (.A(pwmcnt[19]), .B(hcrb[19]), 
         .Z(n6074)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i39_2_lut_rep_312.init = 16'h6666;
    LUT4 i3652_2_lut_3_lut_4_lut (.A(pwmcnt[19]), .B(hcrb[19]), .C(hcrb[18]), 
         .D(pwmcnt[18]), .Z(n4899)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3652_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 pwmcnt_31__I_0_i32_3_lut_3_lut (.A(pwmcnt[19]), .B(hcrb[19]), .C(hcrb[18]), 
         .Z(n32_adj_1012)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i32_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i2179_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[14]), 
         .Z(n1151)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2179_2_lut_4_lut.init = 16'hfe00;
    LUT4 pwmcnt_31__I_0_i41_2_lut_rep_313 (.A(pwmcnt[20]), .B(hcrb[20]), 
         .Z(n6075)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i41_2_lut_rep_313.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_i34_3_lut_3_lut (.A(pwmcnt[20]), .B(hcrb[20]), .C(n32_adj_1012), 
         .Z(n34_adj_1011)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i34_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i4231_2_lut_3_lut (.A(pwmcnt[20]), .B(hcrb[20]), .C(n5442), .Z(n4904)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4231_2_lut_3_lut.init = 16'hf6f6;
    LUT4 LessThan_4_i57_2_lut_rep_252 (.A(tcr[28]), .B(pwmcnt[28]), .Z(n6014)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i57_2_lut_rep_252.init = 16'h6666;
    LUT4 LessThan_4_i50_3_lut_3_lut (.A(tcr[28]), .B(pwmcnt[28]), .C(n22_adj_1003), 
         .Z(n50)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i50_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i2177_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[16]), 
         .Z(n1149)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2177_2_lut_4_lut.init = 16'hfe00;
    LUT4 pwmcnt_31__I_0_i26_3_lut_3_lut (.A(pwmcnt[15]), .B(hcrb[15]), .C(n14), 
         .Z(n26_adj_1025)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i26_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i2200_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[17]), 
         .Z(n1148)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2200_2_lut_4_lut.init = 16'hfe00;
    LUT4 i4230_4_lut (.A(n6074), .B(n6073), .C(n6072), .D(n4874), .Z(n5442)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4230_4_lut.init = 16'hfeff;
    LUT4 i2264_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[18]), 
         .Z(n1147)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2264_2_lut_4_lut.init = 16'hfe00;
    LUT4 pwmcnt_31__I_0_i31_2_lut_rep_316 (.A(pwmcnt[15]), .B(hcrb[15]), 
         .Z(n6078)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i31_2_lut_rep_316.init = 16'h6666;
    LUT4 i3627_4_lut (.A(n6071), .B(n6078), .C(n6077), .D(n4858), .Z(n4874)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3627_4_lut.init = 16'h5455;
    LUT4 i2265_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[19]), 
         .Z(n1146)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2265_2_lut_4_lut.init = 16'hfe00;
    LUT4 pwmcnt_31__I_0_68_i4_4_lut (.A(hcra[0]), .B(hcra[1]), .C(pwmcnt[1]), 
         .D(pwmcnt[0]), .Z(n4_adj_1000)) /* synthesis lut_function=(A (B+!(C))+!A !(B (C (D))+!B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam pwmcnt_31__I_0_68_i4_4_lut.init = 16'h8ecf;
    LUT4 pwmcnt_31__I_0_i13_2_lut_rep_317 (.A(pwmcnt[6]), .B(hcrb[6]), .Z(n6079)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i13_2_lut_rep_317.init = 16'h6666;
    LUT4 i3611_4_lut (.A(n6076), .B(n6083), .C(n6079), .D(n11), .Z(n4858)) /* synthesis lut_function=(!(A+!(B+(C+(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3611_4_lut.init = 16'h5554;
    LUT4 pwmcnt_31__I_0_i51_2_lut_rep_318 (.A(pwmcnt[25]), .B(hcrb[25]), 
         .Z(n6080)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i51_2_lut_rep_318.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_i14_3_lut_3_lut (.A(pwmcnt[14]), .B(hcrb[14]), .C(hcrb[13]), 
         .Z(n14)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i14_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i47_2_lut_rep_253 (.A(tcr[23]), .B(pwmcnt[23]), .Z(n6015)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i47_2_lut_rep_253.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_i29_2_lut_rep_315 (.A(pwmcnt[14]), .B(hcrb[14]), 
         .Z(n6077)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i29_2_lut_rep_315.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_i44_3_lut_3_lut (.A(pwmcnt[25]), .B(hcrb[25]), .C(n42_adj_996), 
         .Z(n44_adj_1019)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i44_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i4217_2_lut_3_lut (.A(pwmcnt[25]), .B(hcrb[25]), .C(n5428), .Z(n4948)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4217_2_lut_3_lut.init = 16'hf6f6;
    LedStatus LedStatus (.clk_c(clk_c), .led_c(led_c), .led_status({led_status}), 
            .GND_net(GND_net)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(30[3] 35[2])
    LUT4 LessThan_4_i49_2_lut_rep_254 (.A(tcr[24]), .B(pwmcnt[24]), .Z(n6016)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i49_2_lut_rep_254.init = 16'h6666;
    LUT4 pwmb_I_2_4_lut (.A(n57), .B(pwmb_N_336), .C(n62_adj_1043), .D(n58_adj_1045), 
         .Z(pwmb_N_334)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[11:40])
    defparam pwmb_I_2_4_lut.init = 16'hccc8;
    LUT4 i2266_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[20]), 
         .Z(n1145)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2266_2_lut_4_lut.init = 16'hff01;
    LUT4 pwmcnt_31__I_0_i53_2_lut_rep_319 (.A(pwmcnt[26]), .B(hcrb[26]), 
         .Z(n6081)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i53_2_lut_rep_319.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_i55_2_lut_rep_320 (.A(pwmcnt[27]), .B(hcrb[27]), 
         .Z(n6082)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i55_2_lut_rep_320.init = 16'h6666;
    LUT4 i2267_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[21]), 
         .Z(n1144)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2267_2_lut_4_lut.init = 16'hff01;
    LUT4 i2268_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[22]), 
         .Z(n1143)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2268_2_lut_4_lut.init = 16'hfe00;
    LUT4 i4220_4_lut (.A(n6026), .B(n6025), .C(n6024), .D(n5270), .Z(n5432)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4220_4_lut.init = 16'hfeff;
    LUT4 i4090_2_lut_3_lut_4_lut (.A(tcr[24]), .B(pwmcnt[24]), .C(pwmcnt[23]), 
         .D(tcr[23]), .Z(n5337)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4090_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 i4023_4_lut (.A(n6023), .B(n6022), .C(n6021), .D(n5254), .Z(n5270)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4023_4_lut.init = 16'h5455;
    LUT4 LessThan_4_i63_2_lut_rep_247 (.A(tcr[31]), .B(pwmcnt[31]), .Z(n6009)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i63_2_lut_rep_247.init = 16'h6666;
    LUT4 i2269_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[23]), 
         .Z(n1142)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2269_2_lut_4_lut.init = 16'hfe00;
    LUT4 pwmcnt_31__I_0_i22_3_lut_3_lut (.A(pwmcnt[27]), .B(hcrb[27]), .C(hcrb[26]), 
         .Z(n22)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i22_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i56_3_lut_3_lut (.A(tcr[31]), .B(pwmcnt[31]), .C(n18_adj_1018), 
         .Z(n56)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i56_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_i15_2_lut_rep_321 (.A(pwmcnt[7]), .B(hcrb[7]), .Z(n6083)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i15_2_lut_rep_321.init = 16'h6666;
    LUT4 i4229_2_lut_3_lut (.A(pwmcnt[20]), .B(hcrb[20]), .C(n5440), .Z(n4906)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4229_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i3634_2_lut_3_lut_4_lut (.A(pwmcnt[7]), .B(hcrb[7]), .C(hcrb[16]), 
         .D(pwmcnt[16]), .Z(n4881)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3634_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 i2270_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[24]), 
         .Z(n1141)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2270_2_lut_4_lut.init = 16'hfe00;
    LUT4 i4007_4_lut (.A(n6032), .B(n6036), .C(n6035), .D(n11_adj_1029), 
         .Z(n5254)) /* synthesis lut_function=(!(A+!(B+(C+(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4007_4_lut.init = 16'h5554;
    LUT4 i25_4_lut_adj_76 (.A(hcrb[0]), .B(n50_adj_1049), .C(n34_adj_1054), 
         .D(hcrb[28]), .Z(n57)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i25_4_lut_adj_76.init = 16'hfffe;
    LUT4 i3558_3_lut_4_lut (.A(pwmcnt[3]), .B(hcrb[3]), .C(hcrb[2]), .D(pwmcnt[2]), 
         .Z(n4805)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3558_3_lut_4_lut.init = 16'h9009;
    LUT4 LessThan_4_i42_3_lut_3_lut (.A(tcr[24]), .B(pwmcnt[24]), .C(pwmcnt[23]), 
         .Z(n42)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i42_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i51_2_lut_rep_255 (.A(tcr[25]), .B(pwmcnt[25]), .Z(n6017)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i51_2_lut_rep_255.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_i64_4_lut (.A(n40_adj_987), .B(n62_adj_981), .C(n6067), 
         .D(n4982), .Z(pwmb_N_336)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i64_4_lut.init = 16'hcacc;
    LUT4 LessThan_4_i44_3_lut_3_lut (.A(tcr[25]), .B(pwmcnt[25]), .C(n42), 
         .Z(n44_adj_1037)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i44_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i30_4_lut_adj_77 (.A(n41_adj_1052), .B(n60_adj_1044), .C(n54_adj_1047), 
         .D(n42_adj_1051), .Z(n62_adj_1043)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i30_4_lut_adj_77.init = 16'hfffe;
    LUT4 i4253_2_lut_3_lut (.A(tcr[31]), .B(pwmcnt[31]), .C(n5464), .Z(n5391)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4253_2_lut_3_lut.init = 16'hf6f6;
    LUT4 pwmcnt_31__I_0_i6_3_lut_3_lut (.A(pwmcnt[3]), .B(hcrb[3]), .C(hcrb[2]), 
         .Z(n6_adj_974)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i6_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i59_2_lut_rep_248 (.A(tcr[29]), .B(pwmcnt[29]), .Z(n6010)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i59_2_lut_rep_248.init = 16'h6666;
    LUT4 i26_4_lut_adj_78 (.A(hcrb[25]), .B(n52_adj_1048), .C(n38_adj_1053), 
         .D(hcrb[26]), .Z(n58_adj_1045)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i26_4_lut_adj_78.init = 16'hfffe;
    LUT4 pwmcnt_31__I_0_i45_2_lut_rep_322 (.A(pwmcnt[22]), .B(hcrb[22]), 
         .Z(n6084)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i45_2_lut_rep_322.init = 16'h6666;
    LUT4 i2271_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[25]), 
         .Z(n1140)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2271_2_lut_4_lut.init = 16'hfe00;
    LUT4 i4210_2_lut_3_lut (.A(tcr[25]), .B(pwmcnt[25]), .C(n5421), .Z(n5344)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4210_2_lut_3_lut.init = 16'hf6f6;
    LUT4 LessThan_4_i41_2_lut_rep_256 (.A(tcr[20]), .B(pwmcnt[20]), .Z(n6018)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i41_2_lut_rep_256.init = 16'h6666;
    LUT4 i2178_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[15]), 
         .Z(n1150)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2178_2_lut_4_lut.init = 16'hfe00;
    LUT4 LessThan_4_i34_3_lut_3_lut (.A(tcr[20]), .B(pwmcnt[20]), .C(n32_adj_994), 
         .Z(n34)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i34_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i4221_2_lut_3_lut (.A(tcr[20]), .B(pwmcnt[20]), .C(n5432), .Z(n5300)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4221_2_lut_3_lut.init = 16'hf6f6;
    LUT4 i4219_2_lut_3_lut (.A(tcr[20]), .B(pwmcnt[20]), .C(n5430), .Z(n5302)) /* synthesis lut_function=(A ((C)+!B)+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4219_2_lut_3_lut.init = 16'hf6f6;
    LUT4 pwmcnt_31__I_0_i24_3_lut_3_lut (.A(pwmcnt[22]), .B(hcrb[22]), .C(n16), 
         .Z(n24_adj_970)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i24_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i20_3_lut_3_lut (.A(tcr[29]), .B(pwmcnt[29]), .C(pwmcnt[12]), 
         .Z(n20_adj_1016)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i20_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i43_2_lut_rep_257 (.A(tcr[21]), .B(pwmcnt[21]), .Z(n6019)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i43_2_lut_rep_257.init = 16'h6666;
    LUT4 LessThan_4_i61_2_lut_rep_249 (.A(tcr[30]), .B(pwmcnt[30]), .Z(n6011)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i61_2_lut_rep_249.init = 16'h6666;
    LUT4 i18_4_lut_adj_79 (.A(hcrb[8]), .B(hcrb[11]), .C(hcrb[16]), .D(hcrb[21]), 
         .Z(n50_adj_1049)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i18_4_lut_adj_79.init = 16'hfffe;
    LUT4 i2_2_lut_adj_80 (.A(hcrb[18]), .B(hcrb[2]), .Z(n34_adj_1054)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[12:19])
    defparam i2_2_lut_adj_80.init = 16'heeee;
    LUT4 pwmcnt_31__I_0_i27_2_lut_rep_314 (.A(pwmcnt[13]), .B(hcrb[13]), 
         .Z(n6076)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i27_2_lut_rep_314.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_i62_4_lut (.A(n48_adj_1023), .B(n60_adj_982), .C(n6067), 
         .D(n4984), .Z(n62_adj_981)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i62_4_lut.init = 16'hcacc;
    LUT4 pwmcnt_31__I_0_i47_2_lut_rep_323 (.A(pwmcnt[23]), .B(hcrb[23]), 
         .Z(n6085)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i47_2_lut_rep_323.init = 16'h6666;
    LUT4 LessThan_4_i54_3_lut_3_lut (.A(tcr[30]), .B(pwmcnt[30]), .C(n20_adj_1016), 
         .Z(n54_adj_997)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i54_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i3735_4_lut (.A(n6070), .B(n6069), .C(n6068), .D(n4955), .Z(n4982)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3735_4_lut.init = 16'h0100;
    LUT4 i3737_4_lut (.A(n6070), .B(n6069), .C(n6068), .D(n4957), .Z(n4984)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3737_4_lut.init = 16'h0100;
    LUT4 i4241_2_lut_3_lut_4_lut (.A(pwmcnt[13]), .B(hcrb[13]), .C(n6078), 
         .D(n6077), .Z(n4872)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i4241_2_lut_3_lut_4_lut.init = 16'hfff6;
    LUT4 pwmcnt_31__I_0_i49_2_lut_rep_324 (.A(pwmcnt[24]), .B(hcrb[24]), 
         .Z(n6086)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i49_2_lut_rep_324.init = 16'h6666;
    LUT4 i4238_4_lut (.A(n6046), .B(n6051), .C(n6050), .D(n5072), .Z(n5450)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4238_4_lut.init = 16'hfeff;
    LUT4 i3694_2_lut_3_lut_4_lut (.A(pwmcnt[24]), .B(hcrb[24]), .C(hcrb[23]), 
         .D(pwmcnt[23]), .Z(n4941)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3694_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 LessThan_4_i16_3_lut_3_lut (.A(tcr[21]), .B(pwmcnt[21]), .C(pwmcnt[9]), 
         .Z(n16_adj_1022)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i16_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i53_2_lut_rep_250 (.A(tcr[26]), .B(pwmcnt[26]), .Z(n6012)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i53_2_lut_rep_250.init = 16'h6666;
    LUT4 i2272_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[26]), 
         .Z(n1139)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2272_2_lut_4_lut.init = 16'hfe00;
    LUT4 LessThan_4_i45_2_lut_rep_258 (.A(tcr[22]), .B(pwmcnt[22]), .Z(n6020)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i45_2_lut_rep_258.init = 16'h6666;
    LUT4 LessThan_4_i24_3_lut_3_lut (.A(tcr[22]), .B(pwmcnt[22]), .C(n16_adj_1022), 
         .Z(n24_adj_1001)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i24_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_i42_3_lut_3_lut (.A(pwmcnt[24]), .B(hcrb[24]), .C(hcrb[23]), 
         .Z(n42_adj_996)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i42_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i29_2_lut_rep_259 (.A(tcr[14]), .B(pwmcnt[14]), .Z(n6021)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i29_2_lut_rep_259.init = 16'h6666;
    LUT4 i3825_4_lut (.A(n6049), .B(n6045), .C(n6044), .D(n5056), .Z(n5072)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3825_4_lut.init = 16'h5455;
    LUT4 i3809_4_lut (.A(n6043), .B(n6059), .C(n6048), .D(n11_adj_988), 
         .Z(n5056)) /* synthesis lut_function=(!(A+!(B+(C+(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3809_4_lut.init = 16'h5554;
    LUT4 i4203_2_lut_3_lut_4_lut (.A(tcr[26]), .B(pwmcnt[26]), .C(n6014), 
         .D(n6013), .Z(n5373)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4203_2_lut_3_lut_4_lut.init = 16'hfff6;
    LUT4 i3708_4_lut (.A(n6082), .B(n6081), .C(n6080), .D(n4926), .Z(n4955)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3708_4_lut.init = 16'h0100;
    LUT4 i4223_2_lut_3_lut_4_lut (.A(tcr[14]), .B(pwmcnt[14]), .C(n6022), 
         .D(n6032), .Z(n5268)) /* synthesis lut_function=(A ((C+(D))+!B)+!A (B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4223_2_lut_3_lut_4_lut.init = 16'hfff6;
    LUT4 pwmcnt_31__I_0_i23_2_lut_rep_325 (.A(pwmcnt[11]), .B(hcrb[11]), 
         .Z(n6087)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i23_2_lut_rep_325.init = 16'h6666;
    LUT4 i3679_4_lut (.A(n6086), .B(n6085), .C(n6084), .D(n4911), .Z(n4926)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3679_4_lut.init = 16'h0100;
    LUT4 pwmcnt_31__I_0_i18_3_lut_3_lut (.A(pwmcnt[11]), .B(hcrb[11]), .C(hcrb[10]), 
         .Z(n18_adj_971)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i18_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i3664_4_lut (.A(n6088), .B(n6075), .C(n6074), .D(n4884), .Z(n4911)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3664_4_lut.init = 16'h5455;
    LUT4 i3637_4_lut (.A(n6073), .B(n6072), .C(n6071), .D(n4861), .Z(n4884)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3637_4_lut.init = 16'h0100;
    PFUMX LessThan_4_i52 (.BLUT(n6), .ALUT(n50), .C0(n5373), .Z(n52));
    LUT4 i3614_4_lut (.A(n6078), .B(n6077), .C(n6076), .D(n4846), .Z(n4861)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3614_4_lut.init = 16'h0001;
    LUT4 LessThan_4_i14_3_lut_3_lut (.A(tcr[14]), .B(pwmcnt[14]), .C(pwmcnt[13]), 
         .Z(n14_adj_1024)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i14_3_lut_3_lut.init = 16'hd4d4;
    LUT4 i3599_4_lut (.A(n25_adj_1026), .B(n6087), .C(n6091), .D(n4827), 
         .Z(n4846)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3599_4_lut.init = 16'h0100;
    LUT4 LessThan_4_i31_2_lut_rep_260 (.A(tcr[15]), .B(pwmcnt[15]), .Z(n6022)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i31_2_lut_rep_260.init = 16'h6666;
    LUT4 i3580_4_lut (.A(n6090), .B(n6089), .C(n6083), .D(n4814), .Z(n4827)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3580_4_lut.init = 16'h1011;
    LUT4 i4226_4_lut (.A(n6042), .B(n6041), .C(n6040), .D(n5164), .Z(n5438)) /* synthesis lut_function=(A+(B+!(C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i4226_4_lut.init = 16'hefee;
    LUT4 i3567_4_lut (.A(n6079), .B(n11), .C(n9_adj_972), .D(n4805), 
         .Z(n4814)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3567_4_lut.init = 16'h1011;
    LUT4 i2273_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[27]), 
         .Z(n1138)) /* synthesis lut_function=(A (D)+!A (B (D)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2273_2_lut_4_lut.init = 16'hfe00;
    LUT4 pwmcnt_31__I_0_i43_2_lut_rep_326 (.A(pwmcnt[21]), .B(hcrb[21]), 
         .Z(n6088)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i43_2_lut_rep_326.init = 16'h6666;
    LUT4 i3917_4_lut (.A(n6054), .B(n6053), .C(n25), .D(n5041), .Z(n5164)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(47[23:39])
    defparam i3917_4_lut.init = 16'h1011;
    LUT4 pwmcnt_31__I_0_i16_3_lut_3_lut (.A(pwmcnt[21]), .B(hcrb[21]), .C(hcrb[9]), 
         .Z(n16)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i16_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i55_2_lut_rep_251 (.A(tcr[27]), .B(pwmcnt[27]), .Z(n6013)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i55_2_lut_rep_251.init = 16'h6666;
    LUT4 pwmcnt_31__I_0_i17_2_lut_rep_327 (.A(pwmcnt[8]), .B(hcrb[8]), .Z(n6089)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i17_2_lut_rep_327.init = 16'h6666;
    LUT4 LessThan_4_i26_3_lut_3_lut (.A(tcr[15]), .B(pwmcnt[15]), .C(n14_adj_1024), 
         .Z(n26)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i26_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_i8_3_lut_3_lut (.A(pwmcnt[8]), .B(hcrb[8]), .C(hcrb[4]), 
         .Z(n8_adj_973)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i8_3_lut_3_lut.init = 16'hd4d4;
    LUT4 LessThan_4_i62_4_lut (.A(n48), .B(n60_adj_992), .C(n6009), .D(n5380), 
         .Z(n62_adj_980)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i62_4_lut.init = 16'hcacc;
    LUT4 i4140_4_lut (.A(n6009), .B(n6011), .C(n6010), .D(n5358), .Z(n5387)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4140_4_lut.init = 16'h0100;
    LUT4 LessThan_4_i33_2_lut_rep_261 (.A(tcr[16]), .B(pwmcnt[16]), .Z(n6023)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i33_2_lut_rep_261.init = 16'h6666;
    LUT4 i2274_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[28]), 
         .Z(n1137)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2274_2_lut_4_lut.init = 16'hff01;
    LUT4 i3710_4_lut (.A(n6082), .B(n6081), .C(n6080), .D(n4937), .Z(n4957)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3710_4_lut.init = 16'h1011;
    PFUMX pwmcnt_31__I_0_68_i28 (.BLUT(n4_adj_1000), .ALUT(n26_adj_1008), 
          .C0(n5070), .Z(n28_adj_1009));
    LUT4 LessThan_4_i12_3_lut_3_lut (.A(tcr[16]), .B(pwmcnt[16]), .C(pwmcnt[7]), 
         .Z(n12_adj_1028)) /* synthesis lut_function=(A (B (C))+!A (B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam LessThan_4_i12_3_lut_3_lut.init = 16'hd4d4;
    LUT4 pwmcnt_31__I_0_i19_2_lut_rep_328 (.A(pwmcnt[9]), .B(hcrb[9]), .Z(n6090)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i19_2_lut_rep_328.init = 16'h6666;
    LUT4 i2275_2_lut_4_lut (.A(n5998), .B(cmd[0]), .C(n6064), .D(cmd_data[29]), 
         .Z(n1136)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(75[5:9])
    defparam i2275_2_lut_4_lut.init = 16'hff01;
    Rst_sys Rst_sys_uu (.rst_n(rst_n), .clk_c(clk_c), .GND_net(GND_net)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(17[10:32])
    LUT4 i4133_4_lut (.A(n6011), .B(n6010), .C(n6014), .D(n5353), .Z(n5380)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4133_4_lut.init = 16'h0100;
    LUT4 i3690_4_lut (.A(n6086), .B(n6085), .C(n6084), .D(n4916), .Z(n4937)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3690_4_lut.init = 16'h0100;
    LUT4 i3669_4_lut (.A(n6088), .B(n25_adj_1026), .C(n6087), .D(n4836), 
         .Z(n4916)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3669_4_lut.init = 16'h5455;
    LUT4 i4106_4_lut (.A(n6013), .B(n6012), .C(n6017), .D(n5333), .Z(n5353)) /* synthesis lut_function=(!(A+(B+!(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4106_4_lut.init = 16'h1011;
    LUT4 i3676_2_lut_3_lut_4_lut (.A(pwmcnt[9]), .B(hcrb[9]), .C(hcrb[21]), 
         .D(pwmcnt[21]), .Z(n4923)) /* synthesis lut_function=(A (B (C (D)+!C !(D)))+!A !(B+!(C (D)+!C !(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3676_2_lut_3_lut_4_lut.init = 16'h9009;
    LUT4 i4086_4_lut (.A(n6016), .B(n6015), .C(n6020), .D(n5312), .Z(n5333)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4086_4_lut.init = 16'h0100;
    LUT4 i3589_4_lut (.A(n6091), .B(n6090), .C(n6089), .D(n9_adj_972), 
         .Z(n4836)) /* synthesis lut_function=(!(A+!(B+(C+(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam i3589_4_lut.init = 16'h5554;
    Debug_core Debug_uut (.clk_c(clk_c), .wr(wr), .wr_data({wr_data}), 
            .rst_n(rst_n), .tx_c(tx_c), .GND_net(GND_net), .rx_c(rx_c), 
            .cmd({cmd}), .cmd_data({cmd_data}), .valid_o(valid_o), .n6711(n6711), 
            .n6065(n6065), .n3413(n3413), .n5993(n5993), .clk_c_enable_90(clk_c_enable_90), 
            .clk_c_enable_213(clk_c_enable_213), .n5387(n5387), .n62(n62_adj_980), 
            .n40(n40), .n984(n984), .clk_c_enable_290(clk_c_enable_290), 
            .n6001(n6001), .n4777(n4777), .clk_c_enable_121(clk_c_enable_121)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(88[3] 99[2])
    LUT4 i4065_4_lut (.A(n6019), .B(n25_adj_999), .C(n6031), .D(n5232), 
         .Z(n5312)) /* synthesis lut_function=(!(A+!(B+(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i4065_4_lut.init = 16'h5455;
    PFUMX pwmcnt_31__I_0_68_i52 (.BLUT(n6_adj_1002), .ALUT(n50_adj_979), 
          .C0(n5175), .Z(n52_adj_978));
    LUT4 pwmcnt_31__I_0_i21_2_lut_rep_329 (.A(pwmcnt[10]), .B(hcrb[10]), 
         .Z(n6091)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(48[23:39])
    defparam pwmcnt_31__I_0_i21_2_lut_rep_329.init = 16'h6666;
    TSALL TSALL_INST (.TSALL(GND_net));
    LUT4 i3985_4_lut (.A(n6030), .B(n6029), .C(n6028), .D(n9_adj_1031), 
         .Z(n5232)) /* synthesis lut_function=(!(A+!(B+(C+(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(45[13:28])
    defparam i3985_4_lut.init = 16'h5554;
    VHI i4514 (.Z(VCC_net));
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module LedStatus
//

module LedStatus (clk_c, led_c, led_status, GND_net) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    output led_c;
    input [2:0]led_status;
    input GND_net;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(3[8:11])
    wire [31:0]cnt;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    
    wire clk_c_enable_61, n2695;
    wire [31:0]n133;
    
    wire clk_c_enable_8, led_N_560, n14, n20, n4698, n5985, n5406, 
        n5927, n5926, n5928, n3595, n5930, n5736, n5738, n4, 
        n4705, n5981, n5407, n5929, n5987, n76, n3812, n3811, 
        n3810, n3809, n3808, n3807, n3806, n3805, n3804, n3799, 
        n3800, n3801, n3802, n10, n5996, n2533, n4_adj_961, n19, 
        n3798, n3797, n3803, n6007, n7, n4658, n3502, n22, n25, 
        n16, n5979, n3926, n4704, n31, n4_adj_962, n3852, n4_adj_963, 
        n4708, n6092, n63, n4694, n2570, n5, n5_adj_964, n9, 
        n4767, n4754, n4735, n4_adj_965, n6003, n72, n4699, n83, 
        n53, n4741, n5986, n4720, n4738, n6004, n4709, n6, n4695, 
        n4764, n4688, n12, n4751, n20_adj_966, n26, n6006, n30, 
        n4_adj_967, n4_adj_968, n84, n4703, n4715, n4736, n3932, 
        n6_adj_969, n3;
    
    FD1P3IX cnt_404__i22 (.D(n133[22]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[22])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i22.GSR = "ENABLED";
    FD1P3IX cnt_404__i28 (.D(n133[28]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[28])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i28.GSR = "ENABLED";
    FD1P3IX cnt_404__i27 (.D(n133[27]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[27])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i27.GSR = "ENABLED";
    FD1P3IX cnt_404__i26 (.D(n133[26]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[26])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i26.GSR = "ENABLED";
    FD1P3AY led_36 (.D(led_N_560), .SP(clk_c_enable_8), .CK(clk_c), .Q(led_c)) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=30, LSE_RLINE=35 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(52[10] 78[8])
    defparam led_36.GSR = "ENABLED";
    LUT4 i707_3_lut_4_lut (.A(n14), .B(cnt[7]), .C(cnt[8]), .D(cnt[9]), 
         .Z(n20)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (C (D))) */ ;
    defparam i707_3_lut_4_lut.init = 16'hf800;
    FD1P3IX cnt_404__i25 (.D(n133[25]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[25])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i25.GSR = "ENABLED";
    FD1P3IX cnt_404__i24 (.D(n133[24]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[24])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i24.GSR = "ENABLED";
    FD1P3IX cnt_404__i21 (.D(n133[21]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[21])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i21.GSR = "ENABLED";
    FD1P3IX cnt_404__i20 (.D(n133[20]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[20])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i20.GSR = "ENABLED";
    FD1P3IX cnt_404__i23 (.D(n133[23]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[23])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i23.GSR = "ENABLED";
    LUT4 i4185_1_lut_4_lut (.A(n4698), .B(n5985), .C(cnt[24]), .D(cnt[23]), 
         .Z(n5406)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C (D))))) */ ;
    defparam i4185_1_lut_4_lut.init = 16'h0313;
    PFUMX i4345 (.BLUT(n5927), .ALUT(n5926), .C0(led_status[1]), .Z(n5928));
    FD1P3IX cnt_404__i19 (.D(n133[19]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i19.GSR = "ENABLED";
    FD1P3IX cnt_404__i31 (.D(n133[31]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[31])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i31.GSR = "ENABLED";
    FD1P3IX cnt_404__i30 (.D(n133[30]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[30])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i30.GSR = "ENABLED";
    FD1P3IX cnt_404__i29 (.D(n133[29]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[29])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i29.GSR = "ENABLED";
    FD1P3IX cnt_404__i18 (.D(n133[18]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i18.GSR = "ENABLED";
    FD1P3IX cnt_404__i17 (.D(n133[17]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i17.GSR = "ENABLED";
    FD1P3IX cnt_404__i16 (.D(n133[16]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i16.GSR = "ENABLED";
    FD1P3IX cnt_404__i15 (.D(n133[15]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i15.GSR = "ENABLED";
    FD1P3IX cnt_404__i14 (.D(n133[14]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i14.GSR = "ENABLED";
    FD1P3IX cnt_404__i13 (.D(n133[13]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i13.GSR = "ENABLED";
    FD1P3IX cnt_404__i12 (.D(n133[12]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i12.GSR = "ENABLED";
    FD1P3IX cnt_404__i11 (.D(n133[11]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i11.GSR = "ENABLED";
    FD1P3IX cnt_404__i10 (.D(n133[10]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i10.GSR = "ENABLED";
    FD1P3IX cnt_404__i9 (.D(n133[9]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i9.GSR = "ENABLED";
    FD1P3IX cnt_404__i8 (.D(n133[8]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i8.GSR = "ENABLED";
    FD1P3IX cnt_404__i7 (.D(n133[7]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i7.GSR = "ENABLED";
    FD1P3IX cnt_404__i6 (.D(n133[6]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i6.GSR = "ENABLED";
    FD1P3IX cnt_404__i5 (.D(n133[5]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i5.GSR = "ENABLED";
    FD1P3IX cnt_404__i4 (.D(n133[4]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i4.GSR = "ENABLED";
    FD1P3IX cnt_404__i3 (.D(n133[3]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i3.GSR = "ENABLED";
    FD1P3IX cnt_404__i2 (.D(n133[2]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i2.GSR = "ENABLED";
    FD1P3IX cnt_404__i1 (.D(n133[1]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i1.GSR = "ENABLED";
    LUT4 n3595_bdd_3_lut_4497 (.A(n3595), .B(led_status[0]), .C(led_status[1]), 
         .Z(n5930)) /* synthesis lut_function=(!(A (B+(C))+!A !((C)+!B))) */ ;
    defparam n3595_bdd_3_lut_4497.init = 16'h5353;
    LUT4 n5736_bdd_4_lut_4353 (.A(n5736), .B(n5738), .C(led_status[0]), 
         .D(cnt[22]), .Z(n5927)) /* synthesis lut_function=(A (B+(C))+!A (B ((D)+!C)+!B (C (D)))) */ ;
    defparam n5736_bdd_4_lut_4353.init = 16'hfcac;
    LUT4 n5736_bdd_3_lut_4352 (.A(n4), .B(cnt[21]), .C(cnt[22]), .Z(n5926)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam n5736_bdd_3_lut_4352.init = 16'hfefe;
    FD1P3IX cnt_404__i0 (.D(n133[0]), .SP(clk_c_enable_61), .CD(n2695), 
            .CK(clk_c), .Q(cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404__i0.GSR = "ENABLED";
    LUT4 i4186_1_lut_4_lut (.A(n4705), .B(n5981), .C(cnt[23]), .D(cnt[22]), 
         .Z(n5407)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C (D))))) */ ;
    defparam i4186_1_lut_4_lut.init = 16'h0313;
    LUT4 n5928_bdd_2_lut_3_lut_4_lut (.A(cnt[24]), .B(n5985), .C(n5928), 
         .D(cnt[23]), .Z(n5929)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(66[24:49])
    defparam n5928_bdd_2_lut_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_3_lut_4_lut (.A(n5987), .B(cnt[8]), .C(cnt[9]), .D(cnt[10]), 
         .Z(n76)) /* synthesis lut_function=(A (B (D)+!B (C (D)))+!A (C (D))) */ ;
    defparam i1_3_lut_4_lut.init = 16'hf800;
    CCU2D cnt_404_add_4_33 (.A0(cnt[31]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3812), .S0(n133[31]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_33.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_33.INIT1 = 16'h0000;
    defparam cnt_404_add_4_33.INJECT1_0 = "NO";
    defparam cnt_404_add_4_33.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_31 (.A0(cnt[29]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[30]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3811), .COUT(n3812), .S0(n133[29]), .S1(n133[30]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_31.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_31.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_31.INJECT1_0 = "NO";
    defparam cnt_404_add_4_31.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_29 (.A0(cnt[27]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[28]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3810), .COUT(n3811), .S0(n133[27]), .S1(n133[28]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_29.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_29.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_29.INJECT1_0 = "NO";
    defparam cnt_404_add_4_29.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_27 (.A0(cnt[25]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[26]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3809), .COUT(n3810), .S0(n133[25]), .S1(n133[26]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_27.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_27.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_27.INJECT1_0 = "NO";
    defparam cnt_404_add_4_27.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_25 (.A0(cnt[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[24]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3808), .COUT(n3809), .S0(n133[23]), .S1(n133[24]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_25.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_25.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_25.INJECT1_0 = "NO";
    defparam cnt_404_add_4_25.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_23 (.A0(cnt[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[22]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3807), .COUT(n3808), .S0(n133[21]), .S1(n133[22]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_23.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_23.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_23.INJECT1_0 = "NO";
    defparam cnt_404_add_4_23.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_21 (.A0(cnt[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[20]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3806), .COUT(n3807), .S0(n133[19]), .S1(n133[20]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_21.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_21.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_21.INJECT1_0 = "NO";
    defparam cnt_404_add_4_21.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_19 (.A0(cnt[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[18]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3805), .COUT(n3806), .S0(n133[17]), .S1(n133[18]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_19.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_19.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_19.INJECT1_0 = "NO";
    defparam cnt_404_add_4_19.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_17 (.A0(cnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3804), .COUT(n3805), .S0(n133[15]), .S1(n133[16]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_17.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_17.INJECT1_0 = "NO";
    defparam cnt_404_add_4_17.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3799), 
          .COUT(n3800), .S0(n133[5]), .S1(n133[6]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_7.INJECT1_0 = "NO";
    defparam cnt_404_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3801), 
          .COUT(n3802), .S0(n133[9]), .S1(n133[10]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_11.INJECT1_0 = "NO";
    defparam cnt_404_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3800), 
          .COUT(n3801), .S0(n133[7]), .S1(n133[8]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_9.INJECT1_0 = "NO";
    defparam cnt_404_add_4_9.INJECT1_1 = "NO";
    LUT4 i5_3_lut_rep_234 (.A(cnt[31]), .B(n10), .C(cnt[28]), .Z(n5996)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i5_3_lut_rep_234.init = 16'hfefe;
    LUT4 i1497_4_lut (.A(clk_c_enable_61), .B(n2533), .C(n4_adj_961), 
         .D(n19), .Z(n2695)) /* synthesis lut_function=(A (B (C)+!B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i1497_4_lut.init = 16'ha2a0;
    LUT4 i1_2_lut_rep_223_4_lut (.A(cnt[31]), .B(n10), .C(cnt[28]), .D(cnt[25]), 
         .Z(n5985)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_2_lut_rep_223_4_lut.init = 16'hfffe;
    CCU2D cnt_404_add_4_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3798), 
          .COUT(n3799), .S0(n133[3]), .S1(n133[4]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_5.INJECT1_0 = "NO";
    defparam cnt_404_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3797), 
          .COUT(n3798), .S0(n133[1]), .S1(n133[2]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_3.INJECT1_0 = "NO";
    defparam cnt_404_add_4_3.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_13 (.A0(cnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3802), .COUT(n3803), .S0(n133[11]), .S1(n133[12]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_13.INJECT1_0 = "NO";
    defparam cnt_404_add_4_13.INJECT1_1 = "NO";
    LUT4 cnt_21__bdd_4_lut_4270 (.A(cnt[21]), .B(cnt[20]), .C(n6007), 
         .D(n7), .Z(n5736)) /* synthesis lut_function=(A (B+(C (D)))) */ ;
    defparam cnt_21__bdd_4_lut_4270.init = 16'ha888;
    CCU2D cnt_404_add_4_15 (.A0(cnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3803), .COUT(n3804), .S0(n133[13]), .S1(n133[14]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_404_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_404_add_4_15.INJECT1_0 = "NO";
    defparam cnt_404_add_4_15.INJECT1_1 = "NO";
    CCU2D cnt_404_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n3797), 
          .S1(n133[0]));   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam cnt_404_add_4_1.INIT0 = 16'hF000;
    defparam cnt_404_add_4_1.INIT1 = 16'h0555;
    defparam cnt_404_add_4_1.INJECT1_0 = "NO";
    defparam cnt_404_add_4_1.INJECT1_1 = "NO";
    PFUMX i38 (.BLUT(n4658), .ALUT(n3502), .C0(led_status[2]), .Z(n19));
    PFUMX i39 (.BLUT(n22), .ALUT(n25), .C0(led_status[0]), .Z(n16));
    LUT4 i1_2_lut (.A(led_status[0]), .B(led_status[1]), .Z(n2533)) /* synthesis lut_function=(A+!(B)) */ ;
    defparam i1_2_lut.init = 16'hbbbb;
    LUT4 i1_4_lut (.A(n5979), .B(n3926), .C(cnt[22]), .D(cnt[21]), .Z(n25)) /* synthesis lut_function=(A+(B (C)+!B (C (D)))) */ ;
    defparam i1_4_lut.init = 16'hfaea;
    LUT4 i1_4_lut_adj_25 (.A(n4704), .B(n5981), .C(cnt[23]), .D(cnt[22]), 
         .Z(n22)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_25.init = 16'hfcec;
    LUT4 i2310_4_lut (.A(cnt[19]), .B(n31), .C(cnt[20]), .D(n4_adj_962), 
         .Z(n3502)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i2310_4_lut.init = 16'hfcec;
    LUT4 i1_4_lut_adj_26 (.A(n3852), .B(n5996), .C(cnt[25]), .D(cnt[24]), 
         .Z(n4658)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_26.init = 16'hfcec;
    PFUMX status_2__I_0_i2 (.BLUT(n5406), .ALUT(n5407), .C0(led_status[0]), 
          .Z(n3595)) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=30, LSE_RLINE=35 */ ;
    LUT4 i1_4_lut_adj_27 (.A(cnt[17]), .B(cnt[20]), .C(cnt[19]), .D(n4_adj_963), 
         .Z(n4)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_27.init = 16'hfcec;
    LUT4 i1_4_lut_adj_28 (.A(n4708), .B(led_status[1]), .C(n16), .D(led_status[2]), 
         .Z(n4_adj_961)) /* synthesis lut_function=(A+!(B+!(C (D)))) */ ;
    defparam i1_4_lut_adj_28.init = 16'hbaaa;
    LUT4 i1_4_lut_adj_29 (.A(cnt[16]), .B(cnt[18]), .C(n6092), .D(n63), 
         .Z(n4_adj_963)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B)) */ ;
    defparam i1_4_lut_adj_29.init = 16'heeec;
    LUT4 i1_4_lut_adj_30 (.A(cnt[11]), .B(cnt[13]), .C(n4694), .D(cnt[12]), 
         .Z(n63)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_30.init = 16'hccc8;
    LUT4 i2_4_lut (.A(led_status[1]), .B(led_status[2]), .C(led_status[0]), 
         .D(n2570), .Z(n4708)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
    defparam i2_4_lut.init = 16'h2000;
    LUT4 i12_3_lut_3_lut (.A(led_status[1]), .B(led_status[0]), .C(led_status[2]), 
         .Z(clk_c_enable_61)) /* synthesis lut_function=(!(A (B (C))+!A !(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(53[9] 77[16])
    defparam i12_3_lut_3_lut.init = 16'h7a7a;
    LUT4 i1_2_lut_rep_330 (.A(cnt[14]), .B(cnt[15]), .Z(n6092)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i1_2_lut_rep_330.init = 16'heeee;
    LUT4 i1_2_lut_adj_31 (.A(cnt[6]), .B(cnt[7]), .Z(n5)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_2_lut_adj_31.init = 16'h8888;
    LUT4 i4215_2_lut_3_lut (.A(led_status[1]), .B(led_status[0]), .C(led_status[2]), 
         .Z(clk_c_enable_8)) /* synthesis lut_function=(!(A (B (C)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(53[9] 77[16])
    defparam i4215_2_lut_3_lut.init = 16'h7f7f;
    LUT4 i1_4_lut_adj_32 (.A(cnt[22]), .B(cnt[21]), .C(cnt[19]), .D(n5_adj_964), 
         .Z(n9)) /* synthesis lut_function=(A (B+(C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_32.init = 16'ha888;
    LUT4 i1_2_lut_3_lut (.A(cnt[14]), .B(cnt[15]), .C(cnt[16]), .Z(n4767)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i1_2_lut_3_lut.init = 16'hfefe;
    LUT4 i1_4_lut_adj_33 (.A(cnt[18]), .B(n4754), .C(n4735), .D(n4_adj_965), 
         .Z(n5_adj_964)) /* synthesis lut_function=(A+(B (C)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_33.init = 16'hfaea;
    LUT4 i1_4_lut_adj_34 (.A(cnt[9]), .B(cnt[14]), .C(n6003), .D(n72), 
         .Z(n4_adj_965)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_34.init = 16'hfcec;
    LUT4 i1_4_lut_adj_35 (.A(n4699), .B(n5985), .C(cnt[24]), .D(cnt[23]), 
         .Z(n2570)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_35.init = 16'hfcec;
    LUT4 i1_4_lut_adj_36 (.A(n83), .B(n53), .C(cnt[20]), .D(n4741), 
         .Z(n4699)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i1_4_lut_adj_36.init = 16'hc8c0;
    LUT4 i1_2_lut_rep_241 (.A(cnt[11]), .B(cnt[10]), .Z(n6003)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_2_lut_rep_241.init = 16'h8888;
    LUT4 i1_3_lut_4_lut_adj_37 (.A(cnt[11]), .B(cnt[10]), .C(cnt[9]), 
         .D(n5986), .Z(n4720)) /* synthesis lut_function=(A (B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_3_lut_4_lut_adj_37.init = 16'h8880;
    LUT4 i1_2_lut_3_lut_adj_38 (.A(cnt[17]), .B(cnt[16]), .C(cnt[18]), 
         .Z(n4738)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i1_2_lut_3_lut_adj_38.init = 16'h8080;
    LUT4 i1_2_lut_adj_39 (.A(cnt[8]), .B(cnt[7]), .Z(n72)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_39.init = 16'h8888;
    LUT4 i1_2_lut_3_lut_adj_40 (.A(cnt[17]), .B(cnt[16]), .C(cnt[15]), 
         .Z(n4735)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i1_2_lut_3_lut_adj_40.init = 16'h8080;
    LUT4 i1_2_lut_adj_41 (.A(cnt[22]), .B(cnt[21]), .Z(n53)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_2_lut_adj_41.init = 16'h8888;
    LUT4 i1_2_lut_rep_242 (.A(cnt[13]), .B(cnt[14]), .Z(n6004)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i1_2_lut_rep_242.init = 16'heeee;
    LUT4 i1_4_lut_adj_42 (.A(n76), .B(n4767), .C(n4709), .D(cnt[11]), 
         .Z(n83)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i1_4_lut_adj_42.init = 16'hfcec;
    LUT4 i1_4_lut_adj_43 (.A(cnt[17]), .B(cnt[16]), .C(n6), .D(cnt[14]), 
         .Z(n7)) /* synthesis lut_function=(A+(B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_43.init = 16'heaaa;
    LUT4 i2_4_lut_adj_44 (.A(cnt[15]), .B(n4754), .C(n4695), .D(cnt[11]), 
         .Z(n6)) /* synthesis lut_function=(A (B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i2_4_lut_adj_44.init = 16'haaa8;
    LUT4 i1_2_lut_3_lut_adj_45 (.A(cnt[13]), .B(cnt[14]), .C(cnt[15]), 
         .Z(n4764)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i1_2_lut_3_lut_adj_45.init = 16'hfefe;
    LUT4 i2_4_lut_adj_46 (.A(cnt[23]), .B(cnt[22]), .C(n4688), .D(cnt[21]), 
         .Z(n3852)) /* synthesis lut_function=(A (B (C+(D)))) */ ;
    defparam i2_4_lut_adj_46.init = 16'h8880;
    LUT4 i1_2_lut_rep_245 (.A(cnt[18]), .B(cnt[19]), .Z(n6007)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_rep_245.init = 16'h8888;
    LUT4 i1_2_lut_3_lut_adj_47 (.A(cnt[18]), .B(cnt[19]), .C(cnt[17]), 
         .Z(n4741)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i1_2_lut_3_lut_adj_47.init = 16'h8080;
    LUT4 cnt_21__bdd_4_lut (.A(cnt[21]), .B(cnt[22]), .C(cnt[20]), .D(n9), 
         .Z(n5738)) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A (C (D))) */ ;
    defparam cnt_21__bdd_4_lut.init = 16'hf808;
    LUT4 i6_4_lut (.A(cnt[2]), .B(n12), .C(cnt[1]), .D(cnt[5]), .Z(n14)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i6_4_lut.init = 16'h8000;
    LUT4 i4_4_lut (.A(cnt[27]), .B(cnt[26]), .C(cnt[29]), .D(cnt[30]), 
         .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i4_4_lut.init = 16'hfffe;
    LUT4 i5_4_lut (.A(cnt[6]), .B(cnt[4]), .C(cnt[3]), .D(cnt[0]), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i5_4_lut.init = 16'h8000;
    LUT4 i1_2_lut_adj_48 (.A(cnt[15]), .B(cnt[16]), .Z(n4751)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i1_2_lut_adj_48.init = 16'heeee;
    LUT4 i666_4_lut (.A(n20_adj_966), .B(cnt[12]), .C(cnt[11]), .D(cnt[10]), 
         .Z(n26)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i666_4_lut.init = 16'hfcec;
    LUT4 i1_3_lut_4_lut_adj_49 (.A(cnt[9]), .B(cnt[10]), .C(cnt[8]), .D(n5), 
         .Z(n4695)) /* synthesis lut_function=(A (B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_3_lut_4_lut_adj_49.init = 16'h8880;
    LUT4 i3_3_lut_4_lut (.A(cnt[9]), .B(cnt[10]), .C(cnt[8]), .D(n5), 
         .Z(n4694)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i3_3_lut_4_lut.init = 16'h8000;
    LUT4 i1_2_lut_rep_244 (.A(cnt[9]), .B(cnt[10]), .Z(n6006)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_2_lut_rep_244.init = 16'h8888;
    LUT4 i1_4_lut_adj_50 (.A(cnt[18]), .B(n30), .C(cnt[17]), .D(n4751), 
         .Z(n4_adj_962)) /* synthesis lut_function=(A+(B (C)+!B (C (D)))) */ ;
    defparam i1_4_lut_adj_50.init = 16'hfaea;
    LUT4 i1_4_lut_adj_51 (.A(cnt[14]), .B(n6006), .C(n4754), .D(n4_adj_967), 
         .Z(n30)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_51.init = 16'ha8a0;
    LUT4 i1_2_lut_adj_52 (.A(cnt[12]), .B(cnt[13]), .Z(n4754)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_2_lut_adj_52.init = 16'heeee;
    LUT4 i2_4_lut_adj_53 (.A(n6007), .B(cnt[20]), .C(n4751), .D(n4_adj_968), 
         .Z(n4688)) /* synthesis lut_function=(A (B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i2_4_lut_adj_53.init = 16'h8880;
    LUT4 i1_4_lut_adj_54 (.A(cnt[14]), .B(cnt[17]), .C(cnt[13]), .D(n26), 
         .Z(n4_adj_968)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i1_4_lut_adj_54.init = 16'heccc;
    LUT4 i1_4_lut_adj_55 (.A(n84), .B(n4703), .C(cnt[19]), .D(n4738), 
         .Z(n4704)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i1_4_lut_adj_55.init = 16'hc8c0;
    LUT4 i1_4_lut_adj_56 (.A(n20), .B(n4764), .C(n4715), .D(cnt[10]), 
         .Z(n84)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_56.init = 16'hfcec;
    LUT4 i1_2_lut_rep_217_3_lut_4_lut (.A(cnt[25]), .B(n5996), .C(cnt[23]), 
         .D(cnt[24]), .Z(n5979)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i1_2_lut_rep_217_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_adj_57 (.A(cnt[12]), .B(cnt[11]), .Z(n4715)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_57.init = 16'h8888;
    LUT4 i1_2_lut_adj_58 (.A(cnt[21]), .B(cnt[20]), .Z(n4703)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_58.init = 16'h8888;
    LUT4 i2_4_lut_adj_59 (.A(cnt[19]), .B(n4736), .C(cnt[20]), .D(cnt[18]), 
         .Z(n3926)) /* synthesis lut_function=(A (B (C)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i2_4_lut_adj_59.init = 16'ha080;
    LUT4 i1_4_lut_adj_60 (.A(cnt[20]), .B(n53), .C(n3932), .D(n4741), 
         .Z(n4698)) /* synthesis lut_function=(A (B)+!A (B (C (D)))) */ ;
    defparam i1_4_lut_adj_60.init = 16'hc888;
    LUT4 i1_4_lut_adj_61 (.A(n6006), .B(n4767), .C(n4709), .D(cnt[11]), 
         .Z(n3932)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(73[56:66])
    defparam i1_4_lut_adj_61.init = 16'hfcec;
    LUT4 i1_2_lut_rep_219_3_lut (.A(cnt[25]), .B(n5996), .C(cnt[24]), 
         .Z(n5981)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i1_2_lut_rep_219_3_lut.init = 16'hfefe;
    LUT4 i725_3_lut_rep_224 (.A(n14), .B(cnt[8]), .C(cnt[7]), .Z(n5986)) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;
    defparam i725_3_lut_rep_224.init = 16'hc8c8;
    LUT4 i1_2_lut_adj_62 (.A(cnt[12]), .B(cnt[13]), .Z(n4709)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(46[16:19])
    defparam i1_2_lut_adj_62.init = 16'h8888;
    LUT4 i1_4_lut_adj_63 (.A(n6_adj_969), .B(n4703), .C(cnt[19]), .D(n4738), 
         .Z(n4705)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i1_4_lut_adj_63.init = 16'hc8c0;
    LUT4 i1_4_lut_adj_64 (.A(cnt[10]), .B(n4764), .C(n4715), .D(n3), 
         .Z(n6_adj_969)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_64.init = 16'hfcec;
    LUT4 i1_2_lut_adj_65 (.A(cnt[8]), .B(cnt[9]), .Z(n3)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_65.init = 16'h8888;
    LUT4 i1_2_lut_4_lut (.A(n14), .B(cnt[8]), .C(cnt[7]), .D(cnt[11]), 
         .Z(n4_adj_967)) /* synthesis lut_function=(A (B (D))+!A (B (C (D)))) */ ;
    defparam i1_2_lut_4_lut.init = 16'hc800;
    LUT4 i1_4_lut_adj_66 (.A(cnt[12]), .B(n4735), .C(n6004), .D(n4720), 
         .Z(n4736)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;
    defparam i1_4_lut_adj_66.init = 16'hccc8;
    LUT4 i661_2_lut_rep_225 (.A(n14), .B(cnt[7]), .Z(n5987)) /* synthesis lut_function=(A (B)) */ ;
    defparam i661_2_lut_rep_225.init = 16'h8888;
    PFUMX i4347 (.BLUT(n5930), .ALUT(n5929), .C0(led_status[2]), .Z(led_N_560));
    LUT4 i1_2_lut_3_lut_4_lut (.A(cnt[23]), .B(n5981), .C(cnt[21]), .D(cnt[22]), 
         .Z(n31)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(66[24:49])
    defparam i1_2_lut_3_lut_4_lut.init = 16'hfffe;
    LUT4 i1_2_lut_3_lut_4_lut_adj_67 (.A(n14), .B(cnt[7]), .C(cnt[9]), 
         .D(cnt[8]), .Z(n20_adj_966)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_67.init = 16'h8000;
    
endmodule
//
// Verilog Description of module Rst_sys
//

module Rst_sys (rst_n, clk_c, GND_net) /* synthesis syn_module_defined=1 */ ;
    output rst_n;
    input clk_c;
    input GND_net;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(3[8:11])
    
    wire n5983;
    wire [10:0]cnt;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(30[25:28])
    
    wire cnt_10__N_364;
    wire [10:0]n49;
    
    wire n3837, n3836, n3835, n3834, n3833, n3544, n3578, n6;
    
    FD1S3AX rst_n_11 (.D(n5983), .CK(clk_c), .Q(rst_n)) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=10, LSE_RCOL=32, LSE_LLINE=17, LSE_RLINE=17 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(40[7] 43[21])
    defparam rst_n_11.GSR = "DISABLED";
    FD1P3AX cnt_403__i0 (.D(n49[0]), .SP(cnt_10__N_364), .CK(clk_c), .Q(cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i0.GSR = "DISABLED";
    FD1P3AX cnt_403__i1 (.D(n49[1]), .SP(cnt_10__N_364), .CK(clk_c), .Q(cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i1.GSR = "DISABLED";
    FD1P3AX cnt_403__i2 (.D(n49[2]), .SP(cnt_10__N_364), .CK(clk_c), .Q(cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i2.GSR = "DISABLED";
    FD1P3AX cnt_403__i3 (.D(n49[3]), .SP(cnt_10__N_364), .CK(clk_c), .Q(cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i3.GSR = "DISABLED";
    FD1P3AX cnt_403__i4 (.D(n49[4]), .SP(cnt_10__N_364), .CK(clk_c), .Q(cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i4.GSR = "DISABLED";
    FD1P3AX cnt_403__i5 (.D(n49[5]), .SP(cnt_10__N_364), .CK(clk_c), .Q(cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i5.GSR = "DISABLED";
    FD1P3AX cnt_403__i6 (.D(n49[6]), .SP(cnt_10__N_364), .CK(clk_c), .Q(cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i6.GSR = "DISABLED";
    FD1P3AX cnt_403__i7 (.D(n49[7]), .SP(cnt_10__N_364), .CK(clk_c), .Q(cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i7.GSR = "DISABLED";
    FD1P3AX cnt_403__i8 (.D(n49[8]), .SP(cnt_10__N_364), .CK(clk_c), .Q(cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i8.GSR = "DISABLED";
    FD1P3AX cnt_403__i9 (.D(n49[9]), .SP(cnt_10__N_364), .CK(clk_c), .Q(cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i9.GSR = "DISABLED";
    FD1P3AX cnt_403__i10 (.D(n49[10]), .SP(cnt_10__N_364), .CK(clk_c), 
            .Q(cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403__i10.GSR = "DISABLED";
    CCU2D cnt_403_add_4_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3837), 
          .S0(n49[9]), .S1(n49[10]));   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_403_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_403_add_4_11.INJECT1_0 = "NO";
    defparam cnt_403_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_403_add_4_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3836), 
          .COUT(n3837), .S0(n49[7]), .S1(n49[8]));   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_403_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_403_add_4_9.INJECT1_0 = "NO";
    defparam cnt_403_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_403_add_4_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3835), 
          .COUT(n3836), .S0(n49[5]), .S1(n49[6]));   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_403_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_403_add_4_7.INJECT1_0 = "NO";
    defparam cnt_403_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_403_add_4_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3834), 
          .COUT(n3835), .S0(n49[3]), .S1(n49[4]));   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_403_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_403_add_4_5.INJECT1_0 = "NO";
    defparam cnt_403_add_4_5.INJECT1_1 = "NO";
    CCU2D cnt_403_add_4_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3833), 
          .COUT(n3834), .S0(n49[1]), .S1(n49[2]));   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_403_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_403_add_4_3.INJECT1_0 = "NO";
    defparam cnt_403_add_4_3.INJECT1_1 = "NO";
    CCU2D cnt_403_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n3833), 
          .S1(n49[0]));   // f:/home/mini-step-fpga/prj/pwm/rst_sys.v(35[12:19])
    defparam cnt_403_add_4_1.INIT0 = 16'hF000;
    defparam cnt_403_add_4_1.INIT1 = 16'h0555;
    defparam cnt_403_add_4_1.INJECT1_0 = "NO";
    defparam cnt_403_add_4_1.INJECT1_1 = "NO";
    LUT4 i2386_4_lut (.A(n3544), .B(cnt[7]), .C(cnt[6]), .D(cnt[5]), 
         .Z(n3578)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i2386_4_lut.init = 16'hc8c0;
    LUT4 i2352_4_lut (.A(cnt[0]), .B(cnt[4]), .C(n6), .D(cnt[3]), .Z(n3544)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i2352_4_lut.init = 16'heccc;
    LUT4 i2_2_lut (.A(cnt[1]), .B(cnt[2]), .Z(n6)) /* synthesis lut_function=(A (B)) */ ;
    defparam i2_2_lut.init = 16'h8888;
    LUT4 i2398_4_lut_rep_221 (.A(cnt[9]), .B(cnt[10]), .C(n3578), .D(cnt[8]), 
         .Z(n5983)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;
    defparam i2398_4_lut_rep_221.init = 16'hccc8;
    LUT4 i2399_1_lut_4_lut (.A(cnt[9]), .B(cnt[10]), .C(n3578), .D(cnt[8]), 
         .Z(cnt_10__N_364)) /* synthesis lut_function=(!(A (B)+!A (B (C+(D))))) */ ;
    defparam i2399_1_lut_4_lut.init = 16'h3337;
    
endmodule
//
// Verilog Description of module Debug_core
//

module Debug_core (clk_c, wr, wr_data, rst_n, tx_c, GND_net, rx_c, 
            cmd, cmd_data, valid_o, n6711, n6065, n3413, n5993, 
            clk_c_enable_90, clk_c_enable_213, n5387, n62, n40, n984, 
            clk_c_enable_290, n6001, n4777, clk_c_enable_121) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    input wr;
    input [31:0]wr_data;
    input rst_n;
    output tx_c;
    input GND_net;
    input rx_c;
    output [7:0]cmd;
    output [31:0]cmd_data;
    output valid_o;
    input n6711;
    output n6065;
    output n3413;
    input n5993;
    output clk_c_enable_90;
    output clk_c_enable_213;
    input n5387;
    input n62;
    input n40;
    output n984;
    output clk_c_enable_290;
    input n6001;
    input n4777;
    output clk_c_enable_121;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(3[8:11])
    wire [2:0]cnt;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(443[11:14])
    
    wire clk_c_enable_228;
    wire [2:0]cnt_2__N_571;
    wire [7:0]tdata;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(447[10:15])
    
    wire clk_c_enable_235;
    wire [31:0]tx_buf;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(455[12:18])
    wire [1:0]cstate;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(227[19:25])
    
    wire n5995, n6005, tx_buf_31__N_680, clk_c_enable_259, n2694, 
        start, n998, n1007, n1008, n1009, n1010, n1011, n1012, 
        n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, 
        n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, 
        n1029, n1030, n6097, n6096;
    wire [1:0]nstate;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(227[27:33])
    
    wire n4674;
    wire [3:0]r_shift_cnt;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(232[17:28])
    
    wire n5988;
    wire [7:0]rx_data;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(438[18:25])
    wire [2:0]cnt_adj_960;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(372[11:14])
    
    wire n5989, clk_c_enable_160;
    wire [2:0]cnt_2__N_883;
    
    wire n4665, cst, n12;
    wire [31:0]nst_N_892;
    
    FD1P3AX cnt_i0 (.D(cnt_2__N_571[0]), .SP(clk_c_enable_228), .CK(clk_c), 
            .Q(cnt[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam cnt_i0.GSR = "ENABLED";
    FD1P3AX tdata_i0_i0 (.D(tx_buf[24]), .SP(clk_c_enable_235), .CK(clk_c), 
            .Q(tdata[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i0.GSR = "DISABLED";
    LUT4 i4248_3_lut_4_lut (.A(cstate[1]), .B(n5995), .C(cnt[2]), .D(n6005), 
         .Z(cnt_2__N_571[2])) /* synthesis lut_function=((B+(C (D)))+!A) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(477[9] 479[12])
    defparam i4248_3_lut_4_lut.init = 16'hfddd;
    LUT4 i1_3_lut_4_lut (.A(cstate[1]), .B(n5995), .C(tx_buf_31__N_680), 
         .D(wr), .Z(clk_c_enable_228)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(477[9] 479[12])
    defparam i1_3_lut_4_lut.init = 16'h2f22;
    FD1P3IX tx_buf_i0_i7 (.D(wr_data[7]), .SP(clk_c_enable_259), .CD(n2694), 
            .CK(clk_c), .Q(tx_buf[7])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i7.GSR = "ENABLED";
    FD1S3AY start_30 (.D(n998), .CK(clk_c), .Q(start));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam start_30.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i0 (.D(wr_data[0]), .SP(clk_c_enable_259), .CD(n2694), 
            .CK(clk_c), .Q(tx_buf[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i0.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i3 (.D(wr_data[3]), .SP(clk_c_enable_259), .CD(n2694), 
            .CK(clk_c), .Q(tx_buf[3])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i3.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i2 (.D(wr_data[2]), .SP(clk_c_enable_259), .CD(n2694), 
            .CK(clk_c), .Q(tx_buf[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i2.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i1 (.D(wr_data[1]), .SP(clk_c_enable_259), .CD(n2694), 
            .CK(clk_c), .Q(tx_buf[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i1.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i6 (.D(wr_data[6]), .SP(clk_c_enable_259), .CD(n2694), 
            .CK(clk_c), .Q(tx_buf[6])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i6.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i5 (.D(wr_data[5]), .SP(clk_c_enable_259), .CD(n2694), 
            .CK(clk_c), .Q(tx_buf[5])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i5.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i4 (.D(wr_data[4]), .SP(clk_c_enable_259), .CD(n2694), 
            .CK(clk_c), .Q(tx_buf[4])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i4.GSR = "ENABLED";
    FD1P3AX cnt_i1 (.D(cnt_2__N_571[1]), .SP(clk_c_enable_228), .CK(clk_c), 
            .Q(cnt[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam cnt_i1.GSR = "ENABLED";
    FD1P3AX cnt_i2 (.D(cnt_2__N_571[2]), .SP(clk_c_enable_228), .CK(clk_c), 
            .Q(cnt[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam cnt_i2.GSR = "ENABLED";
    FD1P3AX tdata_i0_i1 (.D(tx_buf[25]), .SP(clk_c_enable_235), .CK(clk_c), 
            .Q(tdata[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i1.GSR = "DISABLED";
    FD1P3AX tdata_i0_i2 (.D(tx_buf[26]), .SP(clk_c_enable_235), .CK(clk_c), 
            .Q(tdata[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i2.GSR = "DISABLED";
    FD1P3AX tdata_i0_i3 (.D(tx_buf[27]), .SP(clk_c_enable_235), .CK(clk_c), 
            .Q(tdata[3])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i3.GSR = "DISABLED";
    FD1P3AX tdata_i0_i4 (.D(tx_buf[28]), .SP(clk_c_enable_235), .CK(clk_c), 
            .Q(tdata[4])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i4.GSR = "DISABLED";
    FD1P3AX tdata_i0_i5 (.D(tx_buf[29]), .SP(clk_c_enable_235), .CK(clk_c), 
            .Q(tdata[5])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i5.GSR = "DISABLED";
    FD1P3AX tdata_i0_i6 (.D(tx_buf[30]), .SP(clk_c_enable_235), .CK(clk_c), 
            .Q(tdata[6])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i6.GSR = "DISABLED";
    FD1P3AX tdata_i0_i7 (.D(tx_buf[31]), .SP(clk_c_enable_235), .CK(clk_c), 
            .Q(tdata[7])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i7.GSR = "DISABLED";
    FD1P3AX tx_buf_i0_i8 (.D(n1007), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[8])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i8.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i9 (.D(n1008), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[9])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i9.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i10 (.D(n1009), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[10])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i10.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i11 (.D(n1010), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[11])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i11.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i12 (.D(n1011), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[12])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i12.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i13 (.D(n1012), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[13])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i13.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i14 (.D(n1013), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[14])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i14.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i15 (.D(n1014), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[15])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i15.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i16 (.D(n1015), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[16])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i16.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i17 (.D(n1016), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[17])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i17.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i18 (.D(n1017), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[18])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i18.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i19 (.D(n1018), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[19])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i19.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i20 (.D(n1019), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[20])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i20.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i21 (.D(n1020), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[21])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i21.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i22 (.D(n1021), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[22])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i22.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i23 (.D(n1022), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[23])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i23.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i24 (.D(n1023), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[24])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i24.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i25 (.D(n1024), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[25])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i25.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i26 (.D(n1025), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[26])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i26.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i27 (.D(n1026), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[27])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i27.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i28 (.D(n1027), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[28])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i28.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i29 (.D(n1028), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[29])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i29.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i30 (.D(n1029), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[30])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i30.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i31 (.D(n1030), .SP(clk_c_enable_259), .CK(clk_c), 
            .Q(tx_buf[31])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=88, LSE_RLINE=99 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i31.GSR = "ENABLED";
    LUT4 mux_143_i9_3_lut (.A(wr_data[8]), .B(tx_buf[0]), .C(n998), .Z(n1007)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i9_3_lut.init = 16'hcaca;
    LUT4 mux_143_i10_3_lut (.A(wr_data[9]), .B(tx_buf[1]), .C(n998), .Z(n1008)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i10_3_lut.init = 16'hcaca;
    LUT4 mux_143_i11_3_lut (.A(wr_data[10]), .B(tx_buf[2]), .C(n998), 
         .Z(n1009)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i11_3_lut.init = 16'hcaca;
    LUT4 mux_143_i12_3_lut (.A(wr_data[11]), .B(tx_buf[3]), .C(n998), 
         .Z(n1010)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i12_3_lut.init = 16'hcaca;
    LUT4 mux_143_i13_3_lut (.A(wr_data[12]), .B(tx_buf[4]), .C(n998), 
         .Z(n1011)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i13_3_lut.init = 16'hcaca;
    LUT4 mux_143_i14_3_lut (.A(wr_data[13]), .B(tx_buf[5]), .C(n998), 
         .Z(n1012)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i14_3_lut.init = 16'hcaca;
    LUT4 mux_143_i15_3_lut (.A(wr_data[14]), .B(tx_buf[6]), .C(n998), 
         .Z(n1013)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i15_3_lut.init = 16'hcaca;
    LUT4 mux_143_i16_3_lut (.A(wr_data[15]), .B(tx_buf[7]), .C(n998), 
         .Z(n1014)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i16_3_lut.init = 16'hcaca;
    LUT4 mux_143_i17_3_lut (.A(wr_data[16]), .B(tx_buf[8]), .C(n998), 
         .Z(n1015)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i17_3_lut.init = 16'hcaca;
    LUT4 mux_143_i18_3_lut (.A(wr_data[17]), .B(tx_buf[9]), .C(n998), 
         .Z(n1016)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i18_3_lut.init = 16'hcaca;
    LUT4 mux_143_i19_3_lut (.A(wr_data[18]), .B(tx_buf[10]), .C(n998), 
         .Z(n1017)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i19_3_lut.init = 16'hcaca;
    LUT4 mux_143_i20_3_lut (.A(wr_data[19]), .B(tx_buf[11]), .C(n998), 
         .Z(n1018)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i20_3_lut.init = 16'hcaca;
    LUT4 mux_143_i21_3_lut (.A(wr_data[20]), .B(tx_buf[12]), .C(n998), 
         .Z(n1019)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i21_3_lut.init = 16'hcaca;
    LUT4 mux_143_i22_3_lut (.A(wr_data[21]), .B(tx_buf[13]), .C(n998), 
         .Z(n1020)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i22_3_lut.init = 16'hcaca;
    LUT4 mux_143_i23_3_lut (.A(wr_data[22]), .B(tx_buf[14]), .C(n998), 
         .Z(n1021)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i23_3_lut.init = 16'hcaca;
    LUT4 mux_143_i24_3_lut (.A(wr_data[23]), .B(tx_buf[15]), .C(n998), 
         .Z(n1022)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i24_3_lut.init = 16'hcaca;
    LUT4 mux_143_i25_3_lut (.A(wr_data[24]), .B(tx_buf[16]), .C(n998), 
         .Z(n1023)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i25_3_lut.init = 16'hcaca;
    LUT4 mux_143_i26_3_lut (.A(wr_data[25]), .B(tx_buf[17]), .C(n998), 
         .Z(n1024)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i26_3_lut.init = 16'hcaca;
    LUT4 mux_143_i27_3_lut (.A(wr_data[26]), .B(tx_buf[18]), .C(n998), 
         .Z(n1025)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i27_3_lut.init = 16'hcaca;
    LUT4 mux_143_i28_3_lut (.A(wr_data[27]), .B(tx_buf[19]), .C(n998), 
         .Z(n1026)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i28_3_lut.init = 16'hcaca;
    LUT4 mux_143_i29_3_lut (.A(wr_data[28]), .B(tx_buf[20]), .C(n998), 
         .Z(n1027)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i29_3_lut.init = 16'hcaca;
    LUT4 mux_143_i30_3_lut (.A(wr_data[29]), .B(tx_buf[21]), .C(n998), 
         .Z(n1028)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i30_3_lut.init = 16'hcaca;
    LUT4 i1_3_lut_then_3_lut (.A(n5995), .B(cstate[1]), .C(cnt[0]), .Z(n6097)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_3_lut_then_3_lut.init = 16'h4040;
    LUT4 i1_3_lut_else_3_lut (.A(n5995), .B(cstate[1]), .C(cnt[0]), .D(cnt[2]), 
         .Z(n6096)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam i1_3_lut_else_3_lut.init = 16'h0400;
    LUT4 mux_143_i31_3_lut (.A(wr_data[30]), .B(tx_buf[22]), .C(n998), 
         .Z(n1029)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i31_3_lut.init = 16'hcaca;
    LUT4 mux_143_i32_3_lut (.A(wr_data[31]), .B(tx_buf[23]), .C(n998), 
         .Z(n1030)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam mux_143_i32_3_lut.init = 16'hcaca;
    LUT4 i336_4_lut (.A(start), .B(wr), .C(tx_buf_31__N_680), .D(nstate[1]), 
         .Z(clk_c_enable_259)) /* synthesis lut_function=(!(A ((C)+!B)+!A (B (C (D))+!B ((D)+!C)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(471[14] 474[12])
    defparam i336_4_lut.init = 16'h0c5c;
    LUT4 i1496_2_lut (.A(clk_c_enable_259), .B(n998), .Z(n2694)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam i1496_2_lut.init = 16'h8888;
    LUT4 i154_2_lut (.A(n998), .B(rst_n), .Z(clk_c_enable_235)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam i154_2_lut.init = 16'h8888;
    LUT4 i1_4_lut (.A(start), .B(n4674), .C(tx_buf_31__N_680), .D(cstate[1]), 
         .Z(n998)) /* synthesis lut_function=(!(A+!(B (C)+!B !((D)+!C)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam i1_4_lut.init = 16'h4050;
    LUT4 i1_4_lut_adj_24 (.A(r_shift_cnt[0]), .B(r_shift_cnt[3]), .C(r_shift_cnt[2]), 
         .D(r_shift_cnt[1]), .Z(n4674)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam i1_4_lut_adj_24.init = 16'h0400;
    LUT4 i1_2_lut_rep_243 (.A(cnt[0]), .B(cnt[1]), .Z(n6005)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(452[18:29])
    defparam i1_2_lut_rep_243.init = 16'heeee;
    LUT4 i1_2_lut (.A(cnt[2]), .B(cnt[1]), .Z(tx_buf_31__N_680)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(462[10] 480[8])
    defparam i1_2_lut.init = 16'heeee;
    LUT4 i1_2_lut_4_lut_4_lut (.A(cnt[0]), .B(cnt[1]), .C(cnt[2]), .D(n5988), 
         .Z(cnt_2__N_571[0])) /* synthesis lut_function=(!(A+!(B (D)+!B (C (D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(452[18:29])
    defparam i1_2_lut_4_lut_4_lut.init = 16'h5400;
    PFUMX i4362 (.BLUT(n6096), .ALUT(n6097), .C0(cnt[1]), .Z(cnt_2__N_571[1]));
    Debug_core_uart_tx Debug_core_uart_tx_uut (.clk_c(clk_c), .\cstate[1] (cstate[1]), 
            .\nstate[1] (nstate[1]), .tx_c(tx_c), .start(start), .n5995(n5995), 
            .r_shift_cnt({r_shift_cnt}), .GND_net(GND_net), .n5988(n5988), 
            .tdata({tdata})) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(507[3] 515[2])
    Debug_core_uart_rx Debug_core_uart_rx_uut (.clk_c(clk_c), .rx_data({rx_data}), 
            .rx_c(rx_c), .cnt({cnt_adj_960}), .n5989(n5989), .clk_c_enable_160(clk_c_enable_160), 
            .GND_net(GND_net), .cnt_2__N_883({cnt_2__N_883}), .n4665(n4665), 
            .cst(cst), .n12(n12), .\nst_N_892[0] (nst_N_892[0])) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(486[3] 492[2])
    Debug_core_DecodeUart Debug_core_DecodeUart_uut (.cnt({cnt_adj_960}), 
            .clk_c(clk_c), .cnt_2__N_883({cnt_2__N_883}), .cmd({cmd}), 
            .rx_data({rx_data}), .cmd_data({cmd_data}), .cst(cst), .valid_o(valid_o), 
            .n6711(n6711), .clk_c_enable_160(clk_c_enable_160), .n5989(n5989), 
            .n12(n12), .\nst_N_892[0] (nst_N_892[0]), .rst_n(rst_n), .n6065(n6065), 
            .n3413(n3413), .n5993(n5993), .clk_c_enable_90(clk_c_enable_90), 
            .clk_c_enable_213(clk_c_enable_213), .n5387(n5387), .n62(n62), 
            .n40(n40), .n984(n984), .clk_c_enable_290(clk_c_enable_290), 
            .n6001(n6001), .n4777(n4777), .clk_c_enable_121(clk_c_enable_121), 
            .n4665(n4665)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(494[23] 502[2])
    
endmodule
//
// Verilog Description of module Debug_core_uart_tx
//

module Debug_core_uart_tx (clk_c, \cstate[1] , \nstate[1] , tx_c, start, 
            n5995, r_shift_cnt, GND_net, n5988, tdata) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    output \cstate[1] ;
    output \nstate[1] ;
    output tx_c;
    input start;
    output n5995;
    output [3:0]r_shift_cnt;
    input GND_net;
    output n5988;
    input [7:0]tdata;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(3[8:11])
    wire [12:0]r_shift;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(233[18:25])
    
    wire clk_c_enable_130, n2700;
    wire [12:0]r_shift_12__N_934;
    
    wire n2699, n5997;
    wire [12:0]r_shift_12__N_907;
    
    wire r_tx_order_buf, n2475, n6000;
    wire [6:0]r_hold_cnt;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(234[34:44])
    
    wire n6708, n6027, clk_c_enable_122, r_shift_cnt_3__N_933;
    wire [3:0]n21;
    wire [6:0]n33;
    
    wire n6038, n3815, n3814, n3813, n6101, n6709, n4801, n5990, 
        n6100, n4692, n6099;
    
    FD1P3JX r_shift_i12 (.D(r_shift_12__N_934[11]), .SP(clk_c_enable_130), 
            .PD(n2700), .CK(clk_c), .Q(r_shift[11])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i12.GSR = "ENABLED";
    FD1P3JX r_shift_i13 (.D(n5997), .SP(clk_c_enable_130), .PD(n2699), 
            .CK(clk_c), .Q(r_shift[12])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i13.GSR = "ENABLED";
    FD1P3JX r_shift_i11 (.D(r_shift_12__N_934[10]), .SP(clk_c_enable_130), 
            .PD(n2700), .CK(clk_c), .Q(r_shift[10])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i11.GSR = "ENABLED";
    FD1S3AX cstate_i1 (.D(\nstate[1] ), .CK(clk_c), .Q(\cstate[1] )) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(262[13:30])
    defparam cstate_i1.GSR = "ENABLED";
    FD1P3AY r_shift_i1 (.D(r_shift_12__N_907[0]), .SP(clk_c_enable_130), 
            .CK(clk_c), .Q(tx_c)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i1.GSR = "ENABLED";
    FD1S3AX r_tx_order_buf_57 (.D(start), .CK(clk_c), .Q(r_tx_order_buf)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(250[9] 253[12])
    defparam r_tx_order_buf_57.GSR = "ENABLED";
    LUT4 i2_3_lut_rep_331 (.A(n2475), .B(n6000), .C(r_hold_cnt[1]), .Z(n6708)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(306[10:37])
    defparam i2_3_lut_rep_331.init = 16'hfefe;
    LUT4 start_I_0_2_lut_rep_265 (.A(start), .B(r_tx_order_buf), .Z(n6027)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(241[29:54])
    defparam start_I_0_2_lut_rep_265.init = 16'h2222;
    LUT4 i2203_3_lut_3_lut_4_lut (.A(start), .B(r_tx_order_buf), .C(r_shift[1]), 
         .D(\cstate[1] ), .Z(r_shift_12__N_907[0])) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(241[29:54])
    defparam i2203_3_lut_3_lut_4_lut.init = 16'hf0dd;
    LUT4 r_shift_cnt_3__I_15_2_lut_rep_235_3_lut (.A(start), .B(r_tx_order_buf), 
         .C(\cstate[1] ), .Z(n5997)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(241[29:54])
    defparam r_shift_cnt_3__I_15_2_lut_rep_235_3_lut.init = 16'h0202;
    LUT4 mux_744_i1_3_lut_4_lut (.A(start), .B(r_tx_order_buf), .C(\cstate[1] ), 
         .D(n5995), .Z(\nstate[1] )) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(241[29:54])
    defparam mux_744_i1_3_lut_4_lut.init = 16'hf202;
    LUT4 i4207_3_lut_rep_230 (.A(n6000), .B(r_hold_cnt[1]), .C(n2475), 
         .Z(clk_c_enable_122)) /* synthesis lut_function=(!(A+!(B (C)+!B !(C)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(315[10:40])
    defparam i4207_3_lut_rep_230.init = 16'h4141;
    FD1S3IX r_shift_cnt_406__i0 (.D(n21[0]), .CK(clk_c), .CD(r_shift_cnt_3__N_933), 
            .Q(r_shift_cnt[0]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_406__i0.GSR = "ENABLED";
    FD1P3JX r_shift_i10 (.D(r_shift[10]), .SP(clk_c_enable_122), .PD(r_shift_cnt_3__N_933), 
            .CK(clk_c), .Q(r_shift[9])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i10.GSR = "ENABLED";
    FD1P3AY r_shift_i9 (.D(r_shift_12__N_907[8]), .SP(clk_c_enable_130), 
            .CK(clk_c), .Q(r_shift[8])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i9.GSR = "ENABLED";
    FD1P3AY r_shift_i8 (.D(r_shift_12__N_907[7]), .SP(clk_c_enable_130), 
            .CK(clk_c), .Q(r_shift[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i8.GSR = "ENABLED";
    FD1P3AY r_shift_i7 (.D(r_shift_12__N_907[6]), .SP(clk_c_enable_130), 
            .CK(clk_c), .Q(r_shift[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i7.GSR = "ENABLED";
    FD1P3AY r_shift_i6 (.D(r_shift_12__N_907[5]), .SP(clk_c_enable_130), 
            .CK(clk_c), .Q(r_shift[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i6.GSR = "ENABLED";
    FD1P3AY r_shift_i5 (.D(r_shift_12__N_907[4]), .SP(clk_c_enable_130), 
            .CK(clk_c), .Q(r_shift[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i5.GSR = "ENABLED";
    FD1P3AY r_shift_i4 (.D(r_shift_12__N_907[3]), .SP(clk_c_enable_130), 
            .CK(clk_c), .Q(r_shift[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i4.GSR = "ENABLED";
    FD1P3AY r_shift_i3 (.D(r_shift_12__N_907[2]), .SP(clk_c_enable_130), 
            .CK(clk_c), .Q(r_shift[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i3.GSR = "ENABLED";
    FD1P3AY r_shift_i2 (.D(r_shift_12__N_907[1]), .SP(clk_c_enable_130), 
            .CK(clk_c), .Q(r_shift[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam r_shift_i2.GSR = "ENABLED";
    LUT4 i4201_2_lut_4_lut (.A(n6000), .B(r_hold_cnt[1]), .C(n2475), .D(\cstate[1] ), 
         .Z(clk_c_enable_130)) /* synthesis lut_function=(!(A (D)+!A !(B (C+!(D))+!B !(C (D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(315[10:40])
    defparam i4201_2_lut_4_lut.init = 16'h41ff;
    LUT4 i1501_2_lut_4_lut (.A(n6000), .B(r_hold_cnt[1]), .C(n2475), .D(\cstate[1] ), 
         .Z(n2699)) /* synthesis lut_function=(!(A+!(B (C (D))+!B !(C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(315[10:40])
    defparam i1501_2_lut_4_lut.init = 16'h4100;
    FD1S3IX r_hold_cnt_411__i6 (.D(n33[6]), .CK(clk_c), .CD(clk_c_enable_130), 
            .Q(r_hold_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411__i6.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_411__i5 (.D(n33[5]), .CK(clk_c), .CD(clk_c_enable_130), 
            .Q(r_hold_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411__i5.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_411__i4 (.D(n33[4]), .CK(clk_c), .CD(clk_c_enable_130), 
            .Q(r_hold_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411__i4.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_411__i3 (.D(n33[3]), .CK(clk_c), .CD(clk_c_enable_130), 
            .Q(r_hold_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411__i3.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_411__i2 (.D(n33[2]), .CK(clk_c), .CD(clk_c_enable_130), 
            .Q(r_hold_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411__i2.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_411__i1 (.D(n33[1]), .CK(clk_c), .CD(clk_c_enable_130), 
            .Q(r_hold_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411__i1.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_276 (.A(r_shift_cnt[2]), .B(r_shift_cnt[3]), .Z(n6038)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(305[10:27])
    defparam i1_2_lut_rep_276.init = 16'hbbbb;
    LUT4 i2_3_lut_rep_233_4_lut (.A(r_shift_cnt[2]), .B(r_shift_cnt[3]), 
         .C(r_shift_cnt[1]), .D(r_shift_cnt[0]), .Z(n5995)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(305[10:27])
    defparam i2_3_lut_rep_233_4_lut.init = 16'hffbf;
    LUT4 i2_3_lut_4_lut (.A(r_shift_cnt[2]), .B(r_shift_cnt[3]), .C(r_shift_cnt[1]), 
         .D(r_shift_cnt[0]), .Z(n2475)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(305[10:27])
    defparam i2_3_lut_4_lut.init = 16'hfbff;
    CCU2D r_hold_cnt_411_add_4_7 (.A0(r_hold_cnt[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3815), .S0(n33[5]), .S1(n33[6]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411_add_4_7.INIT0 = 16'hfaaa;
    defparam r_hold_cnt_411_add_4_7.INIT1 = 16'hfaaa;
    defparam r_hold_cnt_411_add_4_7.INJECT1_0 = "NO";
    defparam r_hold_cnt_411_add_4_7.INJECT1_1 = "NO";
    CCU2D r_hold_cnt_411_add_4_5 (.A0(r_hold_cnt[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3814), .COUT(n3815), .S0(n33[3]), .S1(n33[4]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411_add_4_5.INIT0 = 16'hfaaa;
    defparam r_hold_cnt_411_add_4_5.INIT1 = 16'hfaaa;
    defparam r_hold_cnt_411_add_4_5.INJECT1_0 = "NO";
    defparam r_hold_cnt_411_add_4_5.INJECT1_1 = "NO";
    CCU2D r_hold_cnt_411_add_4_3 (.A0(r_hold_cnt[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3813), .COUT(n3814), .S0(n33[1]), .S1(n33[2]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411_add_4_3.INIT0 = 16'hfaaa;
    defparam r_hold_cnt_411_add_4_3.INIT1 = 16'hfaaa;
    defparam r_hold_cnt_411_add_4_3.INJECT1_0 = "NO";
    defparam r_hold_cnt_411_add_4_3.INJECT1_1 = "NO";
    CCU2D r_hold_cnt_411_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n3813), .S1(n33[0]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411_add_4_1.INIT0 = 16'hF000;
    defparam r_hold_cnt_411_add_4_1.INIT1 = 16'h0555;
    defparam r_hold_cnt_411_add_4_1.INJECT1_0 = "NO";
    defparam r_hold_cnt_411_add_4_1.INJECT1_1 = "NO";
    LUT4 i1_2_lut_rep_226_4_lut (.A(n6038), .B(r_shift_cnt[0]), .C(r_shift_cnt[1]), 
         .D(\cstate[1] ), .Z(n5988)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(305[10:27])
    defparam i1_2_lut_rep_226_4_lut.init = 16'h1000;
    FD1S3IX r_shift_cnt_406__i1 (.D(n6101), .CK(clk_c), .CD(r_shift_cnt_3__N_933), 
            .Q(r_shift_cnt[1]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_406__i1.GSR = "ENABLED";
    FD1S3IX r_shift_cnt_406__i2 (.D(n6709), .CK(clk_c), .CD(r_shift_cnt_3__N_933), 
            .Q(r_shift_cnt[2]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_406__i2.GSR = "ENABLED";
    FD1S3IX r_shift_cnt_406__i3 (.D(n21[3]), .CK(clk_c), .CD(r_shift_cnt_3__N_933), 
            .Q(r_shift_cnt[3]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_406__i3.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_411__i0 (.D(n33[0]), .CK(clk_c), .CD(clk_c_enable_130), 
            .Q(r_hold_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(321[26:43])
    defparam r_hold_cnt_411__i0.GSR = "ENABLED";
    LUT4 i2_3_lut (.A(r_tx_order_buf), .B(start), .C(\cstate[1] ), .Z(n2700)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(296[9] 330[12])
    defparam i2_3_lut.init = 16'h0404;
    LUT4 i2257_2_lut (.A(r_shift[12]), .B(\cstate[1] ), .Z(r_shift_12__N_934[11])) /* synthesis lut_function=(A (B)) */ ;
    defparam i2257_2_lut.init = 16'h8888;
    LUT4 i3554_4_lut (.A(r_hold_cnt[2]), .B(r_hold_cnt[5]), .C(r_hold_cnt[0]), 
         .D(r_hold_cnt[6]), .Z(n4801)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i3554_4_lut.init = 16'h8000;
    LUT4 cstate_1__I_0_i4_1_lut (.A(\cstate[1] ), .Z(r_shift_cnt_3__N_933)) /* synthesis lut_function=(!(A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(297[16:30])
    defparam cstate_1__I_0_i4_1_lut.init = 16'h5555;
    LUT4 r_shift_12__I_0_i9_4_lut (.A(tdata[7]), .B(r_shift[9]), .C(\cstate[1] ), 
         .D(n6027), .Z(r_shift_12__N_907[8])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i9_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i8_4_lut (.A(tdata[6]), .B(r_shift[8]), .C(\cstate[1] ), 
         .D(n6027), .Z(r_shift_12__N_907[7])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i8_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i7_4_lut (.A(tdata[5]), .B(r_shift[7]), .C(\cstate[1] ), 
         .D(n6027), .Z(r_shift_12__N_907[6])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i7_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i6_4_lut (.A(tdata[4]), .B(r_shift[6]), .C(\cstate[1] ), 
         .D(n6027), .Z(r_shift_12__N_907[5])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i6_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i5_4_lut (.A(tdata[3]), .B(r_shift[5]), .C(\cstate[1] ), 
         .D(n6027), .Z(r_shift_12__N_907[4])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i5_4_lut.init = 16'hcacf;
    LUT4 i2_3_lut_rep_238 (.A(n4801), .B(r_hold_cnt[3]), .C(r_hold_cnt[4]), 
         .Z(n6000)) /* synthesis lut_function=((B+(C))+!A) */ ;
    defparam i2_3_lut_rep_238.init = 16'hfdfd;
    LUT4 r_shift_12__I_0_i4_4_lut (.A(tdata[2]), .B(r_shift[4]), .C(\cstate[1] ), 
         .D(n6027), .Z(r_shift_12__N_907[3])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i4_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i3_4_lut (.A(tdata[1]), .B(r_shift[3]), .C(\cstate[1] ), 
         .D(n6027), .Z(r_shift_12__N_907[2])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i3_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i2_4_lut (.A(tdata[0]), .B(r_shift[2]), .C(\cstate[1] ), 
         .D(n6027), .Z(r_shift_12__N_907[1])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i2_4_lut.init = 16'hcacf;
    LUT4 i1_2_lut_rep_228_4_lut (.A(n4801), .B(r_hold_cnt[3]), .C(r_hold_cnt[4]), 
         .D(r_hold_cnt[1]), .Z(n5990)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
    defparam i1_2_lut_rep_228_4_lut.init = 16'h0200;
    LUT4 r_shift_cnt_0__bdd_4_lut (.A(r_shift_cnt[0]), .B(r_shift_cnt[1]), 
         .C(r_shift_cnt[2]), .D(n5990), .Z(n6709)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;
    defparam r_shift_cnt_0__bdd_4_lut.init = 16'h78f0;
    LUT4 i2255_2_lut (.A(r_shift[11]), .B(\cstate[1] ), .Z(r_shift_12__N_934[10])) /* synthesis lut_function=(A (B)) */ ;
    defparam i2255_2_lut.init = 16'h8888;
    LUT4 i2576_2_lut_3_lut_4_lut_4_lut_then_4_lut (.A(n2475), .B(n6000), 
         .C(r_hold_cnt[1]), .D(r_shift_cnt[1]), .Z(n6100)) /* synthesis lut_function=(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(314[10] 322[8])
    defparam i2576_2_lut_3_lut_4_lut_4_lut_then_4_lut.init = 16'hdf21;
    LUT4 i2590_3_lut (.A(r_shift_cnt[3]), .B(n4692), .C(n6708), .Z(n21[3])) /* synthesis lut_function=(!(A (B)+!A !(B (C)+!B !(C)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(314[10] 322[8])
    defparam i2590_3_lut.init = 16'h6363;
    LUT4 i2576_2_lut_3_lut_4_lut_4_lut_else_4_lut (.A(n2475), .B(n6000), 
         .C(r_hold_cnt[1]), .D(r_shift_cnt[1]), .Z(n6099)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(314[10] 322[8])
    defparam i2576_2_lut_3_lut_4_lut_4_lut_else_4_lut.init = 16'hff01;
    LUT4 i3_4_lut (.A(r_shift_cnt[2]), .B(r_shift_cnt[0]), .C(r_shift_cnt[1]), 
         .D(n5990), .Z(n4692)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(314[10] 322[8])
    defparam i3_4_lut.init = 16'h8000;
    LUT4 i2568_2_lut_3_lut_4_lut (.A(n2475), .B(n5990), .C(n6708), .D(r_shift_cnt[0]), 
         .Z(n21[0])) /* synthesis lut_function=(!(A (B (C (D))+!B !(C (D)))+!A !(C (D)))) */ ;
    defparam i2568_2_lut_3_lut_4_lut.init = 16'h7888;
    PFUMX i4364 (.BLUT(n6099), .ALUT(n6100), .C0(r_shift_cnt[0]), .Z(n6101));
    
endmodule
//
// Verilog Description of module Debug_core_uart_rx
//

module Debug_core_uart_rx (clk_c, rx_data, rx_c, cnt, n5989, clk_c_enable_160, 
            GND_net, cnt_2__N_883, n4665, cst, n12, \nst_N_892[0] ) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    output [7:0]rx_data;
    input rx_c;
    input [2:0]cnt;
    output n5989;
    output clk_c_enable_160;
    input GND_net;
    output [2:0]cnt_2__N_883;
    input n4665;
    input cst;
    output n12;
    output \nst_N_892[0] ;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(3[8:11])
    wire [3:0]r_shift_cnt;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(69[17:28])
    
    wire clk_c_enable_17, n2705;
    wire [3:0]n21;
    
    wire clk_c_enable_226;
    wire [9:0]r_shift;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(70[17:24])
    wire [6:0]r_sample_cnt;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(62[34:46])
    
    wire clk_c_enable_60, n2926;
    wire [6:0]n1;
    
    wire n3919;
    wire [1:0]nstate_1__N_721;
    
    wire r_uart_rx_falling_N_795, busy_f, n6066, r_uart_rx_buf;
    wire [2:0]n1502;
    wire [1:0]nstate_1__N_719;
    
    wire n1962, n6034, n1967, clk_c_enable_219, n3914, n5994, n4653, 
        n2925, n3841, n3840, n3839, n33, n4;
    
    FD1P3IX r_shift_cnt_407__i3 (.D(n21[3]), .SP(clk_c_enable_17), .CD(n2705), 
            .CK(clk_c), .Q(r_shift_cnt[3]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(146[36:54])
    defparam r_shift_cnt_407__i3.GSR = "ENABLED";
    FD1P3IX r_shift_cnt_407__i2 (.D(n21[2]), .SP(clk_c_enable_17), .CD(n2705), 
            .CK(clk_c), .Q(r_shift_cnt[2]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(146[36:54])
    defparam r_shift_cnt_407__i2.GSR = "ENABLED";
    FD1P3IX r_shift_cnt_407__i1 (.D(n21[1]), .SP(clk_c_enable_17), .CD(n2705), 
            .CK(clk_c), .Q(r_shift_cnt[1]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(146[36:54])
    defparam r_shift_cnt_407__i1.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i0 (.D(r_shift[1]), .SP(clk_c_enable_226), .CK(clk_c), 
            .Q(rx_data[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i0.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_409__i6 (.D(n1[6]), .SP(clk_c_enable_60), .CD(n2926), 
            .CK(clk_c), .Q(r_sample_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409__i6.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_409__i1 (.D(n1[1]), .SP(clk_c_enable_60), .CD(n2926), 
            .CK(clk_c), .Q(r_sample_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409__i1.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_409__i5 (.D(n1[5]), .SP(clk_c_enable_60), .CD(n2926), 
            .CK(clk_c), .Q(r_sample_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409__i5.GSR = "ENABLED";
    FD1P3IX r_shift_cnt_407__i0 (.D(n3919), .SP(clk_c_enable_17), .CD(n2705), 
            .CK(clk_c), .Q(r_shift_cnt[0]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(146[36:54])
    defparam r_shift_cnt_407__i0.GSR = "ENABLED";
    FD1S3AX r_uart_rx_falling_62 (.D(r_uart_rx_falling_N_795), .CK(clk_c), 
            .Q(nstate_1__N_721[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(90[9] 93[12])
    defparam r_uart_rx_falling_62.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_409__i4 (.D(n1[4]), .SP(clk_c_enable_60), .CD(n2926), 
            .CK(clk_c), .Q(r_sample_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409__i4.GSR = "ENABLED";
    FD1S3AX busy_f_70 (.D(n6066), .CK(clk_c), .Q(busy_f)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(191[8] 193[6])
    defparam busy_f_70.GSR = "ENABLED";
    FD1S3AX r_uart_rx_buf_61 (.D(rx_c), .CK(clk_c), .Q(r_uart_rx_buf)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(90[9] 93[12])
    defparam r_uart_rx_buf_61.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_409__i3 (.D(n1[3]), .SP(clk_c_enable_60), .CD(n2926), 
            .CK(clk_c), .Q(r_sample_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409__i3.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_409__i2 (.D(n1[2]), .SP(clk_c_enable_60), .CD(n2926), 
            .CK(clk_c), .Q(r_sample_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409__i2.GSR = "ENABLED";
    FD1S3IX cstate_FSM_i2 (.D(n1502[1]), .CK(clk_c), .CD(nstate_1__N_719[0]), 
            .Q(n1502[2]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(111[9] 126[17])
    defparam cstate_FSM_i2.GSR = "ENABLED";
    FD1S3AX cstate_FSM_i1 (.D(n1962), .CK(clk_c), .Q(n1502[1]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(111[9] 126[17])
    defparam cstate_FSM_i1.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_409__i0 (.D(n1[0]), .SP(clk_c_enable_60), .CD(n2926), 
            .CK(clk_c), .Q(r_sample_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409__i0.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_272 (.A(cnt[0]), .B(cnt[1]), .Z(n6034)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(46[12:16])
    defparam i1_2_lut_rep_272.init = 16'h8888;
    LUT4 i1_2_lut_3_lut_4_lut (.A(cnt[0]), .B(cnt[1]), .C(n5989), .D(cnt[2]), 
         .Z(clk_c_enable_160)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(46[12:16])
    defparam i1_2_lut_3_lut_4_lut.init = 16'h0080;
    FD1S3JX cstate_FSM_i0 (.D(n1967), .CK(clk_c), .PD(n1502[2]), .Q(n1502[0]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(111[9] 126[17])
    defparam cstate_FSM_i0.GSR = "ENABLED";
    FD1P3JX r_shift__0__i9 (.D(rx_c), .SP(clk_c_enable_219), .PD(n2705), 
            .CK(clk_c), .Q(r_shift[9]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i9.GSR = "ENABLED";
    FD1P3JX r_shift__0__i8 (.D(r_shift[9]), .SP(clk_c_enable_219), .PD(n2705), 
            .CK(clk_c), .Q(r_shift[8]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i8.GSR = "ENABLED";
    FD1P3JX r_shift__0__i7 (.D(r_shift[8]), .SP(clk_c_enable_219), .PD(n2705), 
            .CK(clk_c), .Q(r_shift[7]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i7.GSR = "ENABLED";
    FD1P3JX r_shift__0__i6 (.D(r_shift[7]), .SP(clk_c_enable_219), .PD(n2705), 
            .CK(clk_c), .Q(r_shift[6]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i6.GSR = "ENABLED";
    FD1P3JX r_shift__0__i5 (.D(r_shift[6]), .SP(clk_c_enable_219), .PD(n2705), 
            .CK(clk_c), .Q(r_shift[5]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i5.GSR = "ENABLED";
    FD1P3JX r_shift__0__i4 (.D(r_shift[5]), .SP(clk_c_enable_219), .PD(n2705), 
            .CK(clk_c), .Q(r_shift[4]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i4.GSR = "ENABLED";
    FD1P3JX r_shift__0__i3 (.D(r_shift[4]), .SP(clk_c_enable_219), .PD(n2705), 
            .CK(clk_c), .Q(r_shift[3]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i3.GSR = "ENABLED";
    FD1P3JX r_shift__0__i2 (.D(r_shift[3]), .SP(clk_c_enable_219), .PD(n2705), 
            .CK(clk_c), .Q(r_shift[2]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i2.GSR = "ENABLED";
    FD1P3JX r_shift__0__i1 (.D(r_shift[2]), .SP(clk_c_enable_219), .PD(n2705), 
            .CK(clk_c), .Q(r_shift[1]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i1.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i7 (.D(r_shift[8]), .SP(clk_c_enable_226), .CK(clk_c), 
            .Q(rx_data[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i7.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i6 (.D(r_shift[7]), .SP(clk_c_enable_226), .CK(clk_c), 
            .Q(rx_data[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i6.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i5 (.D(r_shift[6]), .SP(clk_c_enable_226), .CK(clk_c), 
            .Q(rx_data[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i5.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i4 (.D(r_shift[5]), .SP(clk_c_enable_226), .CK(clk_c), 
            .Q(rx_data[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i4.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i3 (.D(r_shift[4]), .SP(clk_c_enable_226), .CK(clk_c), 
            .Q(rx_data[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i3.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i2 (.D(r_shift[3]), .SP(clk_c_enable_226), .CK(clk_c), 
            .Q(rx_data[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i2.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i1 (.D(r_shift[2]), .SP(clk_c_enable_226), .CK(clk_c), 
            .Q(rx_data[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i1.GSR = "ENABLED";
    LUT4 i2542_2_lut_rep_232 (.A(n3914), .B(r_shift_cnt[0]), .Z(n5994)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(146[36:54])
    defparam i2542_2_lut_rep_232.init = 16'h4444;
    LUT4 i8_4_lut (.A(n4653), .B(r_sample_cnt[2]), .C(r_sample_cnt[4]), 
         .D(r_sample_cnt[6]), .Z(n2925)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam i8_4_lut.init = 16'h0400;
    LUT4 i3_4_lut (.A(r_sample_cnt[2]), .B(r_sample_cnt[6]), .C(r_sample_cnt[4]), 
         .D(n4653), .Z(n3914)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(151[8:38])
    defparam i3_4_lut.init = 16'hffef;
    CCU2D r_sample_cnt_409_add_4_7 (.A0(r_sample_cnt[5]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(r_sample_cnt[6]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n3841), .S0(n1[5]), .S1(n1[6]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409_add_4_7.INIT0 = 16'hfaaa;
    defparam r_sample_cnt_409_add_4_7.INIT1 = 16'hfaaa;
    defparam r_sample_cnt_409_add_4_7.INJECT1_0 = "NO";
    defparam r_sample_cnt_409_add_4_7.INJECT1_1 = "NO";
    CCU2D r_sample_cnt_409_add_4_5 (.A0(r_sample_cnt[3]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(r_sample_cnt[4]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n3840), .COUT(n3841), .S0(n1[3]), 
          .S1(n1[4]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409_add_4_5.INIT0 = 16'hfaaa;
    defparam r_sample_cnt_409_add_4_5.INIT1 = 16'hfaaa;
    defparam r_sample_cnt_409_add_4_5.INJECT1_0 = "NO";
    defparam r_sample_cnt_409_add_4_5.INJECT1_1 = "NO";
    CCU2D r_sample_cnt_409_add_4_3 (.A0(r_sample_cnt[1]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(r_sample_cnt[2]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n3839), .COUT(n3840), .S0(n1[1]), 
          .S1(n1[2]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409_add_4_3.INIT0 = 16'hfaaa;
    defparam r_sample_cnt_409_add_4_3.INIT1 = 16'hfaaa;
    defparam r_sample_cnt_409_add_4_3.INJECT1_0 = "NO";
    defparam r_sample_cnt_409_add_4_3.INJECT1_1 = "NO";
    CCU2D r_sample_cnt_409_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_sample_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n3839), .S1(n1[0]));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(172[37:56])
    defparam r_sample_cnt_409_add_4_1.INIT0 = 16'hF000;
    defparam r_sample_cnt_409_add_4_1.INIT1 = 16'h0555;
    defparam r_sample_cnt_409_add_4_1.INJECT1_0 = "NO";
    defparam r_sample_cnt_409_add_4_1.INJECT1_1 = "NO";
    LUT4 i1_4_lut (.A(r_sample_cnt[3]), .B(r_sample_cnt[0]), .C(r_sample_cnt[1]), 
         .D(r_sample_cnt[5]), .Z(n4653)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(151[8:38])
    defparam i1_4_lut.init = 16'hbfff;
    LUT4 i2555_2_lut_3_lut_4_lut (.A(n3914), .B(r_shift_cnt[0]), .C(r_shift_cnt[2]), 
         .D(r_shift_cnt[1]), .Z(n21[2])) /* synthesis lut_function=(A (C)+!A !(B (C (D)+!C !(D))+!B !(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(146[36:54])
    defparam i2555_2_lut_3_lut_4_lut.init = 16'hb4f0;
    LUT4 i2548_2_lut_3_lut (.A(n3914), .B(r_shift_cnt[0]), .C(r_shift_cnt[1]), 
         .Z(n21[1])) /* synthesis lut_function=(A (C)+!A !(B (C)+!B !(C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(146[36:54])
    defparam i2548_2_lut_3_lut.init = 16'hb4b4;
    LUT4 i1789_3_lut (.A(cnt[0]), .B(busy_f), .C(n1502[0]), .Z(cnt_2__N_883[0])) /* synthesis lut_function=(!(A (B (C))+!A !(B (C)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(46[12:16])
    defparam i1789_3_lut.init = 16'h6a6a;
    LUT4 i1_2_lut (.A(n1502[0]), .B(nstate_1__N_721[0]), .Z(n1967)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(111[9] 126[17])
    defparam i1_2_lut.init = 16'h2222;
    LUT4 i2297_4_lut (.A(cnt[2]), .B(busy_f), .C(n1502[0]), .D(n6034), 
         .Z(cnt_2__N_883[2])) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;
    defparam i2297_4_lut.init = 16'h6aaa;
    LUT4 i2303_4_lut (.A(cnt[1]), .B(busy_f), .C(cnt[0]), .D(n1502[0]), 
         .Z(cnt_2__N_883[1])) /* synthesis lut_function=(!(A (B (C (D)))+!A !(B (C (D))))) */ ;
    defparam i2303_4_lut.init = 16'h6aaa;
    PFUMX i1728 (.BLUT(n33), .ALUT(n2925), .C0(n1502[1]), .Z(n2926));
    LUT4 i1_2_lut_adj_19 (.A(n1502[1]), .B(n1502[2]), .Z(clk_c_enable_226)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(111[9] 126[17])
    defparam i1_2_lut_adj_19.init = 16'h4444;
    LUT4 i1_2_lut_rep_240_3_lut (.A(n1502[0]), .B(n1502[2]), .C(n1502[1]), 
         .Z(n2705)) /* synthesis lut_function=(!(A ((C)+!B)+!A (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(111[9] 126[17])
    defparam i1_2_lut_rep_240_3_lut.init = 16'h0d0d;
    LUT4 i1_2_lut_3_lut (.A(n1502[0]), .B(n1502[2]), .C(n1502[1]), .Z(clk_c_enable_17)) /* synthesis lut_function=((B+(C))+!A) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(111[9] 126[17])
    defparam i1_2_lut_3_lut.init = 16'hfdfd;
    LUT4 i1_2_lut_3_lut_3_lut_4_lut (.A(n1502[0]), .B(n1502[2]), .C(n3914), 
         .D(n1502[1]), .Z(clk_c_enable_219)) /* synthesis lut_function=(!(A (B (C (D))+!B (C+!(D)))+!A (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(111[9] 126[17])
    defparam i1_2_lut_3_lut_3_lut_4_lut.init = 16'h0fdd;
    LUT4 i3_4_lut_adj_20 (.A(r_sample_cnt[6]), .B(clk_c_enable_17), .C(nstate_1__N_721[0]), 
         .D(n4), .Z(clk_c_enable_60)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(111[9] 126[17])
    defparam i3_4_lut_adj_20.init = 16'hfdff;
    LUT4 i1_3_lut (.A(r_sample_cnt[5]), .B(r_sample_cnt[3]), .C(r_sample_cnt[4]), 
         .Z(n4)) /* synthesis lut_function=(A (B+(C))) */ ;
    defparam i1_3_lut.init = 16'ha8a8;
    LUT4 busy_I_0_1_lut_rep_304 (.A(n1502[0]), .Z(n6066)) /* synthesis lut_function=(!(A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(76[19:48])
    defparam busy_I_0_1_lut_rep_304.init = 16'h5555;
    LUT4 i1_3_lut_3_lut (.A(n1502[0]), .B(nstate_1__N_721[0]), .C(n1502[2]), 
         .Z(n33)) /* synthesis lut_function=(!(A ((C)+!B)+!A (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(76[19:48])
    defparam i1_3_lut_3_lut.init = 16'h0d0d;
    LUT4 i1_2_lut_adj_21 (.A(n3914), .B(r_shift_cnt[0]), .Z(n3919)) /* synthesis lut_function=(A (B)+!A !(B)) */ ;
    defparam i1_2_lut_adj_21.init = 16'h9999;
    LUT4 i2_4_lut (.A(r_shift_cnt[1]), .B(r_shift_cnt[0]), .C(r_shift_cnt[3]), 
         .D(r_shift_cnt[2]), .Z(nstate_1__N_719[0])) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;
    defparam i2_4_lut.init = 16'hffdf;
    LUT4 i1_4_lut_adj_22 (.A(n1502[0]), .B(n1502[1]), .C(nstate_1__N_721[0]), 
         .D(nstate_1__N_719[0]), .Z(n1962)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(46[12:16])
    defparam i1_4_lut_adj_22.init = 16'heca0;
    LUT4 i1_3_lut_rep_227_4_lut (.A(n1502[0]), .B(busy_f), .C(n4665), 
         .D(cst), .Z(n5989)) /* synthesis lut_function=(A (B (C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam i1_3_lut_rep_227_4_lut.init = 16'h8880;
    LUT4 i4_3_lut_4_lut (.A(n1502[0]), .B(busy_f), .C(cst), .D(rx_data[6]), 
         .Z(n12)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A !(C+!(D))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam i4_3_lut_4_lut.init = 16'h8f00;
    LUT4 i1_2_lut_3_lut_adj_23 (.A(n1502[0]), .B(busy_f), .C(n4665), .Z(\nst_N_892[0] )) /* synthesis lut_function=(A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(141[9] 181[12])
    defparam i1_2_lut_3_lut_adj_23.init = 16'h8080;
    LUT4 i2562_3_lut_4_lut (.A(r_shift_cnt[1]), .B(n5994), .C(r_shift_cnt[2]), 
         .D(r_shift_cnt[3]), .Z(n21[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(146[36:54])
    defparam i2562_3_lut_4_lut.init = 16'h7f80;
    LUT4 r_uart_rx_falling_I_10_2_lut (.A(rx_c), .B(r_uart_rx_buf), .Z(r_uart_rx_falling_N_795)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(92[25:46])
    defparam r_uart_rx_falling_I_10_2_lut.init = 16'h4444;
    
endmodule
//
// Verilog Description of module Debug_core_DecodeUart
//

module Debug_core_DecodeUart (cnt, clk_c, cnt_2__N_883, cmd, rx_data, 
            cmd_data, cst, valid_o, n6711, clk_c_enable_160, n5989, 
            n12, \nst_N_892[0] , rst_n, n6065, n3413, n5993, clk_c_enable_90, 
            clk_c_enable_213, n5387, n62, n40, n984, clk_c_enable_290, 
            n6001, n4777, clk_c_enable_121, n4665) /* synthesis syn_module_defined=1 */ ;
    output [2:0]cnt;
    input clk_c;
    input [2:0]cnt_2__N_883;
    output [7:0]cmd;
    input [7:0]rx_data;
    output [31:0]cmd_data;
    output cst;
    output valid_o;
    input n6711;
    input clk_c_enable_160;
    input n5989;
    input n12;
    input \nst_N_892[0] ;
    input rst_n;
    output n6065;
    output n3413;
    input n5993;
    output clk_c_enable_90;
    output clk_c_enable_213;
    input n5387;
    input n62;
    input n40;
    output n984;
    output clk_c_enable_290;
    input n6001;
    input n4777;
    output clk_c_enable_121;
    output n4665;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/pwm/top.v(3[8:11])
    
    wire n1604, clk_c_enable_182, clk_c_enable_175, nst, clk_c_enable_152, 
        clk_c_enable_134, clk_c_enable_168, n6037, n4675, n4799;
    wire [31:0]nst_N_893;
    
    wire n14, n4781;
    
    FD1S3IX cnt_i0 (.D(cnt_2__N_883[0]), .CK(clk_c), .CD(n1604), .Q(cnt[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cnt_i0.GSR = "ENABLED";
    FD1P3AX cmd_i0 (.D(rx_data[0]), .SP(clk_c_enable_182), .CK(clk_c), 
            .Q(cmd[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cmd_i0.GSR = "ENABLED";
    FD1P3AX data_i0 (.D(rx_data[0]), .SP(clk_c_enable_175), .CK(clk_c), 
            .Q(cmd_data[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i0.GSR = "ENABLED";
    FD1S3AX cst_70 (.D(nst), .CK(clk_c), .Q(cst)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(379[9:21])
    defparam cst_70.GSR = "ENABLED";
    FD1P3AX data_i31 (.D(rx_data[7]), .SP(clk_c_enable_152), .CK(clk_c), 
            .Q(cmd_data[31])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i31.GSR = "ENABLED";
    FD1P3IX valid_o_72 (.D(n6711), .SP(clk_c_enable_134), .CD(n1604), 
            .CK(clk_c), .Q(valid_o));   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam valid_o_72.GSR = "ENABLED";
    FD1P3AX data_i30 (.D(rx_data[6]), .SP(clk_c_enable_152), .CK(clk_c), 
            .Q(cmd_data[30])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i30.GSR = "ENABLED";
    FD1P3AX data_i29 (.D(rx_data[5]), .SP(clk_c_enable_152), .CK(clk_c), 
            .Q(cmd_data[29])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i29.GSR = "ENABLED";
    FD1P3AX data_i28 (.D(rx_data[4]), .SP(clk_c_enable_152), .CK(clk_c), 
            .Q(cmd_data[28])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i28.GSR = "ENABLED";
    FD1P3AX data_i27 (.D(rx_data[3]), .SP(clk_c_enable_152), .CK(clk_c), 
            .Q(cmd_data[27])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i27.GSR = "ENABLED";
    FD1P3AX data_i26 (.D(rx_data[2]), .SP(clk_c_enable_152), .CK(clk_c), 
            .Q(cmd_data[26])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i26.GSR = "ENABLED";
    FD1P3AX data_i25 (.D(rx_data[1]), .SP(clk_c_enable_152), .CK(clk_c), 
            .Q(cmd_data[25])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i25.GSR = "ENABLED";
    FD1P3AX data_i24 (.D(rx_data[0]), .SP(clk_c_enable_152), .CK(clk_c), 
            .Q(cmd_data[24])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i24.GSR = "ENABLED";
    FD1P3AX data_i23 (.D(rx_data[7]), .SP(clk_c_enable_160), .CK(clk_c), 
            .Q(cmd_data[23])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i23.GSR = "ENABLED";
    FD1P3AX data_i22 (.D(rx_data[6]), .SP(clk_c_enable_160), .CK(clk_c), 
            .Q(cmd_data[22])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i22.GSR = "ENABLED";
    FD1P3AX data_i21 (.D(rx_data[5]), .SP(clk_c_enable_160), .CK(clk_c), 
            .Q(cmd_data[21])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i21.GSR = "ENABLED";
    FD1P3AX data_i20 (.D(rx_data[4]), .SP(clk_c_enable_160), .CK(clk_c), 
            .Q(cmd_data[20])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i20.GSR = "ENABLED";
    FD1P3AX data_i19 (.D(rx_data[3]), .SP(clk_c_enable_160), .CK(clk_c), 
            .Q(cmd_data[19])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i19.GSR = "ENABLED";
    FD1P3AX data_i18 (.D(rx_data[2]), .SP(clk_c_enable_160), .CK(clk_c), 
            .Q(cmd_data[18])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i18.GSR = "ENABLED";
    FD1P3AX data_i17 (.D(rx_data[1]), .SP(clk_c_enable_160), .CK(clk_c), 
            .Q(cmd_data[17])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i17.GSR = "ENABLED";
    FD1P3AX data_i16 (.D(rx_data[0]), .SP(clk_c_enable_160), .CK(clk_c), 
            .Q(cmd_data[16])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i16.GSR = "ENABLED";
    FD1P3AX data_i15 (.D(rx_data[7]), .SP(clk_c_enable_168), .CK(clk_c), 
            .Q(cmd_data[15])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i15.GSR = "ENABLED";
    FD1P3AX data_i14 (.D(rx_data[6]), .SP(clk_c_enable_168), .CK(clk_c), 
            .Q(cmd_data[14])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i14.GSR = "ENABLED";
    FD1P3AX data_i13 (.D(rx_data[5]), .SP(clk_c_enable_168), .CK(clk_c), 
            .Q(cmd_data[13])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i13.GSR = "ENABLED";
    FD1P3AX data_i12 (.D(rx_data[4]), .SP(clk_c_enable_168), .CK(clk_c), 
            .Q(cmd_data[12])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i12.GSR = "ENABLED";
    FD1P3AX data_i11 (.D(rx_data[3]), .SP(clk_c_enable_168), .CK(clk_c), 
            .Q(cmd_data[11])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i11.GSR = "ENABLED";
    FD1P3AX data_i10 (.D(rx_data[2]), .SP(clk_c_enable_168), .CK(clk_c), 
            .Q(cmd_data[10])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i10.GSR = "ENABLED";
    FD1P3AX data_i9 (.D(rx_data[1]), .SP(clk_c_enable_168), .CK(clk_c), 
            .Q(cmd_data[9])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i9.GSR = "ENABLED";
    FD1P3AX data_i8 (.D(rx_data[0]), .SP(clk_c_enable_168), .CK(clk_c), 
            .Q(cmd_data[8])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i8.GSR = "ENABLED";
    FD1P3AX data_i7 (.D(rx_data[7]), .SP(clk_c_enable_175), .CK(clk_c), 
            .Q(cmd_data[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i7.GSR = "ENABLED";
    FD1P3AX data_i6 (.D(rx_data[6]), .SP(clk_c_enable_175), .CK(clk_c), 
            .Q(cmd_data[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i6.GSR = "ENABLED";
    FD1P3AX data_i5 (.D(rx_data[5]), .SP(clk_c_enable_175), .CK(clk_c), 
            .Q(cmd_data[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i5.GSR = "ENABLED";
    FD1P3AX data_i4 (.D(rx_data[4]), .SP(clk_c_enable_175), .CK(clk_c), 
            .Q(cmd_data[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i4.GSR = "ENABLED";
    FD1P3AX data_i3 (.D(rx_data[3]), .SP(clk_c_enable_175), .CK(clk_c), 
            .Q(cmd_data[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i3.GSR = "ENABLED";
    FD1P3AX data_i2 (.D(rx_data[2]), .SP(clk_c_enable_175), .CK(clk_c), 
            .Q(cmd_data[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i2.GSR = "ENABLED";
    FD1P3AX data_i1 (.D(rx_data[1]), .SP(clk_c_enable_175), .CK(clk_c), 
            .Q(cmd_data[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam data_i1.GSR = "ENABLED";
    FD1P3AX cmd_i7 (.D(rx_data[7]), .SP(clk_c_enable_182), .CK(clk_c), 
            .Q(cmd[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cmd_i7.GSR = "ENABLED";
    FD1P3AX cmd_i6 (.D(rx_data[6]), .SP(clk_c_enable_182), .CK(clk_c), 
            .Q(cmd[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cmd_i6.GSR = "ENABLED";
    FD1P3AX cmd_i5 (.D(rx_data[5]), .SP(clk_c_enable_182), .CK(clk_c), 
            .Q(cmd[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cmd_i5.GSR = "ENABLED";
    FD1P3AX cmd_i4 (.D(rx_data[4]), .SP(clk_c_enable_182), .CK(clk_c), 
            .Q(cmd[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cmd_i4.GSR = "ENABLED";
    FD1P3AX cmd_i3 (.D(rx_data[3]), .SP(clk_c_enable_182), .CK(clk_c), 
            .Q(cmd[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cmd_i3.GSR = "ENABLED";
    FD1P3AX cmd_i2 (.D(rx_data[2]), .SP(clk_c_enable_182), .CK(clk_c), 
            .Q(cmd[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cmd_i2.GSR = "ENABLED";
    FD1P3AX cmd_i1 (.D(rx_data[1]), .SP(clk_c_enable_182), .CK(clk_c), 
            .Q(cmd[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cmd_i1.GSR = "ENABLED";
    FD1S3IX cnt_i2 (.D(cnt_2__N_883[2]), .CK(clk_c), .CD(n1604), .Q(cnt[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cnt_i2.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_275 (.A(cnt[1]), .B(cnt[0]), .Z(n6037)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam i1_2_lut_rep_275.init = 16'h2222;
    FD1S3IX cnt_i1 (.D(cnt_2__N_883[1]), .CK(clk_c), .CD(n1604), .Q(cnt[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam cnt_i1.GSR = "ENABLED";
    LUT4 i1_2_lut_3_lut_4_lut (.A(cnt[1]), .B(cnt[0]), .C(n5989), .D(cnt[2]), 
         .Z(clk_c_enable_152)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam i1_2_lut_3_lut_4_lut.init = 16'h0020;
    LUT4 i2_3_lut_4_lut (.A(cnt[1]), .B(n5989), .C(cnt[0]), .D(cnt[2]), 
         .Z(clk_c_enable_182)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
    defparam i2_3_lut_4_lut.init = 16'h0040;
    LUT4 i2_3_lut_4_lut_adj_16 (.A(cnt[1]), .B(n5989), .C(cnt[0]), .D(cnt[2]), 
         .Z(clk_c_enable_168)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam i2_3_lut_4_lut_adj_16.init = 16'h0400;
    LUT4 i3_4_lut (.A(cnt[2]), .B(n4675), .C(rx_data[2]), .D(n6037), 
         .Z(clk_c_enable_134)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(386[19:30])
    defparam i3_4_lut.init = 16'h8000;
    LUT4 i7_4_lut (.A(n4799), .B(rx_data[4]), .C(n12), .D(rx_data[1]), 
         .Z(n4675)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(386[19:30])
    defparam i7_4_lut.init = 16'h0040;
    LUT4 i3552_4_lut (.A(rx_data[3]), .B(rx_data[5]), .C(rx_data[7]), 
         .D(rx_data[0]), .Z(n4799)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
    defparam i3552_4_lut.init = 16'hfeff;
    PFUMX nst_I_12 (.BLUT(\nst_N_892[0] ), .ALUT(nst_N_893[0]), .C0(cst), 
          .Z(nst)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;
    LUT4 i18_2_lut_3_lut (.A(cnt[0]), .B(cnt[2]), .C(cnt[1]), .Z(nst_N_893[0])) /* synthesis lut_function=(!(A (B (C)))) */ ;
    defparam i18_2_lut_3_lut.init = 16'h7f7f;
    LUT4 rst_n_I_0_1_lut_rep_303 (.A(rst_n), .Z(n6065)) /* synthesis lut_function=(!(A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(48[8:14])
    defparam rst_n_I_0_1_lut_rep_303.init = 16'h5555;
    LUT4 i2221_2_lut_3_lut_3_lut (.A(rst_n), .B(cmd[2]), .C(valid_o), 
         .Z(n3413)) /* synthesis lut_function=(A (B (C))+!A (B)) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(48[8:14])
    defparam i2221_2_lut_3_lut_3_lut.init = 16'hc4c4;
    LUT4 i420_3_lut_4_lut_4_lut (.A(rst_n), .B(cmd[0]), .C(n5993), .D(cmd[1]), 
         .Z(clk_c_enable_90)) /* synthesis lut_function=((B (C (D)))+!A) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(48[8:14])
    defparam i420_3_lut_4_lut_4_lut.init = 16'hd555;
    LUT4 i419_3_lut_4_lut_4_lut (.A(rst_n), .B(cmd[0]), .C(n5993), .D(cmd[1]), 
         .Z(clk_c_enable_213)) /* synthesis lut_function=(!(A (B+!(C (D))))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(48[8:14])
    defparam i419_3_lut_4_lut_4_lut.init = 16'h7555;
    LUT4 i129_4_lut_4_lut (.A(rst_n), .B(n5387), .C(n62), .D(n40), .Z(n984)) /* synthesis lut_function=((B (D)+!B (C))+!A) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(48[8:14])
    defparam i129_4_lut_4_lut.init = 16'hfd75;
    LUT4 i423_2_lut_rep_237_2_lut (.A(rst_n), .B(valid_o), .Z(clk_c_enable_290)) /* synthesis lut_function=((B)+!A) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(48[8:14])
    defparam i423_2_lut_rep_237_2_lut.init = 16'hdddd;
    LUT4 i421_4_lut_4_lut (.A(rst_n), .B(n6001), .C(cmd[2]), .D(n4777), 
         .Z(clk_c_enable_121)) /* synthesis lut_function=(!(A (((D)+!C)+!B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/ledstatus.v(48[8:14])
    defparam i421_4_lut_4_lut.init = 16'h55d5;
    LUT4 i7_4_lut_adj_17 (.A(rx_data[4]), .B(n14), .C(n4781), .D(rx_data[1]), 
         .Z(n4665)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam i7_4_lut_adj_17.init = 16'h0400;
    LUT4 i6_4_lut (.A(rx_data[7]), .B(rx_data[3]), .C(rx_data[5]), .D(rx_data[2]), 
         .Z(n14)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(399[10] 418[8])
    defparam i6_4_lut.init = 16'h0080;
    LUT4 i3534_2_lut (.A(rx_data[0]), .B(rx_data[6]), .Z(n4781)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i3534_2_lut.init = 16'heeee;
    LUT4 i1_2_lut_3_lut_4_lut_adj_18 (.A(cnt[0]), .B(cnt[2]), .C(n5989), 
         .D(cnt[1]), .Z(clk_c_enable_175)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ;
    defparam i1_2_lut_3_lut_4_lut_adj_18.init = 16'h0080;
    LUT4 i427_1_lut (.A(nst), .Z(n1604)) /* synthesis lut_function=(!(A)) */ ;   // f:/home/mini-step-fpga/prj/pwm/debug_core.v(384[4] 388[11])
    defparam i427_1_lut.init = 16'h5555;
    
endmodule
//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

